Analog Devices LTM4683 Manual page 90

LTM4683
PMBus COMMAND DETAILS
BIT
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
This command has one data byte.
MFR_PWM_CONFIG
The MFR_PWM_CONFIG command sets the switching frequency phase offset to the falling edge of the SYNC signal.
The part must be in the Off state to process this command. The RUN pins must be low, or the channels must be com-
manded off. If either channel is in the RUN state and this command is written, the command will be NACK'd and a
BUSY fault will be asserted.
BIT MEANING
7 Reserved
[6:5] Input current sense gain
00b 2x gain. 0mV to 50mV range
01b 4x gain. 0mV to 25mV range
10b 8x gain. 0mV to 10mV range
11b Reserved
4 Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
V > VIN_ON. The SHARE_CLK pin will be
IN
pulled low when V
CLK pin will not be pulled low when V
for the initial application of V
3 Reserved
BIT [2:0] CHANNEL 0 (DEGREES)
000b 0
001b 90
010b 0
011b 0
100b 120
101b 60
110b 120
90
MEANING
8
9
11
13
15
17
20
24
28
32
38
46
54
62
< VIN_OFF. If this bit is 0, the SHARE_
IN
< VIN_OFF except
IN
.
IN
CHANNEL 1 (DEGREES)
180
270
240
120
240
240
300
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Rev. 0