Power-Up And Initialization - Analog Devices LTM4683 Manual

OPERATION
only after an invalid CRC has been detected. The chip will
also respond at the global addresses 0x5A and 0x5B, but
using these addresses when attempting to recover from
a CRC issue is not recommended. All power supply rails
associated with either PWM channel of a device reporting
an invalid CRC should remain disabled until the issue is
resolved. See the Applications Information section or con-
tact the factory for details on efficient in-system EEPROM
programming, including bulk EEPROM programming,
which the LTM4683 also supports.
The LTM4683 contains two dual internal constant fre-
quency current mode control buck regulators (Channels
0 and 1 and Channels 2 and 3) whose power MOSFETs
are capable of fast switching speed. Reference to the sig-
nal pins will be Name_nn, where n is either 01 or 23, or
with Namen when referring to signal pins that are related
to the actual channel. The factory NVM-default switching
frequency clocks SYNC_nn at 425kHz, to which the regu-
lators synchronize their switching frequency. The default
phase-interleaving angle between the channels is 180°. A
pin-strapping resistor on FSWPH_nn_CFG configures the
frequency of the SYNC_nn clock (switching frequency) and
the channel phase relationship of the channels to each other
and for the falling edge of the SYNC_nn signal. (Most pos-
sible combinations of switching frequency and phase-angle
assignments are settleable by resistor pin programming;
see Table 3. Configure the LTM4683's NVM to implement
settings not available by resistor-pin strapping.) When an
FSWPH_nn_CFG pin-strap resistor sets the channel phase
relationship of the LTM4683's channels, the SYNC_nn clock
is not driven by the module; instead, SYNC_nn becomes
strictly a high-impedance input, and the channel switching
frequency is then synchronized to SYNC_nn provided by
an externally-generated clock or sibling LTM4683 with a
pull-up resistor to V
DD33_nn
the phase relationship can be altered via the I
but only when the switching action is off, i.e., when the
module is not regulating the outputs. See the Applications
Information section for details.
Programmable analog feedback loop compensation for
Channel 0 to Channel 3 is accomplished with a capaci-
tor connection from COMPna to SGND and a capacitor
from COMPnb to SGND.) The COMPnb pin is for the
. The switching frequency and
2
C interface,
For more information
high-frequency gain roll-off and is the g
put that has a programmable range, and the COMPna
pin has the programmable resistor range along with a
capacitor to SGND that sets the frequency compensa-
tion. See the Programmable Loop Compensation section.
The LTM4683 module has sufficient stability margins and
good transient performance with a wide range of output
capacitors—even all-ceramic MLCCs. Table 13 provides
guidance on input and output capacitors recommended
for many common operating conditions, along with
the programmable compensation settings. The Analog
Devices LTpowerCAD tool is available for transient and
®
stability analysis, and experienced users who prefer to
adjust the module's feedback loop compensation param-
eters can use this tool.

POWER-UP AND INITIALIZATION

The LTM4683 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off operation.
It operates from a single input supply (4.5V to 14V) while
three on-chip linear regulators generate internal 2.5V,
3.3V, and 5.5V per controller. If V
5.75V, and the V pin is turned off, the INTV
BIAS
and SV pins must be connected together. The con-
IN_nn
troller configuration is initialized by an internal threshold-
based UVLO where V
INnn
the 5.5V, 3.3V, and 2.5V linear regulators must be within
approximately 20% of the regulated values. In addition
to the power supply, a PMBus RESTORE_USER_ALL or
MFR_RESET command can initialize the part too.
The V pin is the output of an internal 5.5V buck regula-
BIAS
tor to improve the efficiency of the circuit and minimize
power loss on the LTM4683. The V
approximately 4.8V, and the V
the INTV LDO operates from the V
CC
regulator is powered from V
RUNP .
During initialization, the external configuration resistors
are identified and/or contents of the NVM are read into the
controller's commands, and the power train is held off. The
RUNn and FAULTn, and PGOODn are held low. The LTM4683
will use the contents of Table 1–Table 5 to determine the
resistor-defined parameters. See the R
www.analog.com
LTM4683
amplifier out-
m
does not exceed
INnn
, V
CC
must be approximately 4V, and
pin must exceed
BIAS
must exceed 7V before
IN
pin. The V
BIAS
and enabled with
IN_VBIAS
(Resistor
CONFIG
29
,
INnn
BIAS
Rev. 0