Open-Drain Pins; Phase-Locked Loop And Frequency Synchronization - Analog Devices LTM4683 Manual

APPLICATIONS INFORMATION

OPEN-DRAIN PINS

The LTM4683 has the following open-drain pins:
3.3V Pins
1. FAULTn
2. SYNC_nn
3. SHARE_CLK_nn
4. PGOODn
5.5V Pins (5.5V pins operate correctly when pulled to
3.3V.)
1. RUNn
2. ALERT_nn
3. SCL_nn
4. SDA_nn
All the above open-drain pins have on-chip pull-down
transistors that can sink 3mA at 0.4V. The low threshold
on the pins is 0.8V; thus, there is plenty of margin on the
digital signals with 3mA of current. For 3.3V pins, 3mA
of current is a 1.1k resistor. Unless there are transient
speed issues associated with the RC time constant of the
resistor pull-up and parasitic capacitance to ground, a 10k
resistor or larger is generally recommended.
For high-speed signals such as the SDA, SCL, and SYNC,
a lower-value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 of the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA_nn and
SCL_nn pins with the time constant set to 1/3 of the rise
time is given by Equation 5.
t
RISE
= = 1k
R
PULLUP
3 •100pF
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capaci-
tance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is a one-time constant. The
SYNC_nn pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
oscillator is set for 500kHz, the load is 100pF, and a 3×
time constant is required, the resistor calculation is given
by Equation 6.
R
PULLUP
The closest 1% resistor is 4.99k.
If timing errors occur or if the SYNC frequency is not as
fast as desired, monitor the waveform and determine if the
RC time constant is too long for the application. If pos-
sible, reduce the parasitic capacitance. If not, reduce the
pull-up resistor sufficiently to ensure proper timing. The
SHARE_CLK_nn pull-up resistor has a similar equation
with a period of 10µs and a pull-down time of 1µs. The
RC time constant should be approximately 3µs or faster.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTM4683 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of the
SYNC_nn pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_CONFIG command.
For PolyPhase applications, it is recommended that all
the phases be spaced evenly. Thus, for a 2-phase system,
the signals should be 180° out of phase, and a 4-phase
system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit a false lock to the harmonics of the external clock.
(5)
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter net-
work. The PLL lock range is guaranteed between 250kHz and
1MHz. Nominal parts will have a range beyond this; however,
the operation to a wider frequency range is not guaranteed.
The PLL has a lock detection circuit. If the PLL
should lose lock during the operation, bit 4 of the
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2µs – 500ns
= = 5k
3 •100pF
LTM4683
(6)
Rev. 0
61