Analog Devices LTM4683 Manual page 16

LTM4683
PIN FUNCTIONS
VOUT2_CFG (AA8): Output Voltage Select Pin for V
Coarse Setting. If the VOUT2_CFG and VTRIM2_CFG pins
are both left open—or, if the LTM4683 is configured to
ignore pin-strap (R
CONFIG
ALL[6] = 1b—then the LTM4683s target V
voltage setting (VOUT_COMMAND2) and associated
power-good and OV/UV warning and fault thresholds are
dictated at SV power-up according to the LTM4683's
IN_23
NVM contents. A resistor divider connected to 2.5V and
SGND to this pin—in combination with resistor pin set-
tings on VTRIM2_CFG, and using the factory-default NVM
setting of MFR_CONFIG_ALL[6] = 0b—can be used to
configure the LTM4683's Channel 2 output to power-
up to a VOUT_COMMAND value (and associated output
voltage monitoring and protection/fault-detection thresh-
olds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from VOUT2_CFG to SGND and/or VTRIM2_CFG to SGND
in this manner allows a convenient way to configure mul-
tiple LTM4683s with identical NVM contents for different
output voltage settings all without GUI intervention or
the need to custom-preprogram module NVM contents.
Minimize capacitance especially when the pin is left open
to ensure accurate detection of the pin state. Note that
using R s on VOUT2_CFG/VTRIM2_CFG can affect
CONFIG
the V range setting (MFR_PWM_MODE0[1]) and loop
OUT2
gain. For addressed ASEL_23, Page 0x00 corresponds to
Channel 2, and Page 0x01 corresponds to Channel 3. See
PAGE description section.
FSWPH_23_CFG (AA9): Switching Frequency, Channel
Phase-Interleaving Angle and Phase Relationship to SYNC
Configuration Pin for Channel 2 and Channel 3. If this pin
is left open—or, if the LTM4683 is configured to ignore
pin-strap (R ) resistors, i.e., MFR_CONFIG_ALL[6] =
CONFIG
1b—then LTM4683's switching frequency (FREQUENCY_
SWITCH) and channel phase relationships (with respect
to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated
at SV power-up according to the LTM4683's NVM
IN_23
contents for Channel 2 and Channel 3. Default factory val-
ues are 425kHz operation, Channel 2 at 0°, and Channel 3
at 180°C (convention throughout this document: a phase
angle of 0° means the channel's switch node rises coinci-
dent with the falling edge of the SYNC pulse). Connecting a
16
) resistors, i.e., MFR_CONFIG_
output
OUT2
For more information
, resistor divider from 2.5V to SGND (and using the factory-
OUT2
default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows
a convenient way to configure multiple LTM4683s with
identical NVM contents for different switching frequencies
of operation and phase interleaving angle settings of intra-
and extra-module-paralleled channels—all, without GUI
intervention or the need to custom pre-program module
NVM contents. (See the Applications Information sec-
tion.) Minimize capacitance—especially when the pin is
left open—to ensure accurate detection of the pin state.
ASEL_23 (AA10): Serial Bus Address Configuration Pin
for Channel 2 and Channel 3 Controller. On any given I
SMBus serial bus segment, every device must have its
unique subordinate address. If this pin is left open, the
LTM4683 powers up to its default subordinate address
of 0x4F (hexadecimal), i.e., 1001111b (industry-stan-
dard convention is used throughout this document:
7-bit subordinate addressing). The lower four bits of the
LTM4683's subordinate address can be altered from this
default value by connecting a resistor from this pin to
SGND. Minimize capacitance—especially when the pin is
left open—to ensure accurate detection of the pin state. It
is recommended to use a resistor to set the address. The
ASEL_23 address will be used to address Channels 2 and
3, and a different ASEL_01 address will be used to address
Channel 0 and Channel 1. For addressed ASEL_23, Page
0x00 corresponds to Channel 2, and Page 0x01 corre-
sponds to Channel 3. See PAGE description section. The
GUI will represent Channel 2 as U1:B0 and Channel 3 as
U1:B1. See Figure 32.
VOUT3_CFG (AB8): Output Voltage Select Pin for V
Coarse Setting. If the VOUT3_CFG and VTRIM3_CFG pins
are both left open—or, if the LTM4683 is configured to
ignore pin-strap (R
ALL[6] = 1b—then the LTM4683s target V
voltage setting (VOUT_COMMAND3) and associated
power-good and OV/UV warning and fault thresholds are
dictated at SV
IN_23
NVM contents. A resistor divider connected to 2.5V and
SGND to this pin—in combination with resistor pin set-
tings on VTRIM3_CFG, and using the factory-default NVM
setting of MFR_CONFIG_ALL[6] = 0b—can be used to
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) resistors, i.e., MFR_CONFIG_
CONFIG
power-up according to the LTM4683's
2
C/
,
OUT3
output
OUT3
Rev. 0