Config_All[6] = 1B) Top Resistor = 14.3K - Analog Devices LTM4683 Manual

OPERATION
will occur. If the user does not wish to see the ALERT from
a PLL_FAULT, even if there is not a valid synchronization
signal at power-up, the ALERT mask for PLL_FAULT must
be written. See the description on SMBALERT_MASK for
more details. If the SYNC_nn pin is connected between
multiple ICs, only one of the ICs should have the SYNC_nn
pin enabled using the MFR_CONFIG_ALL[4] = 0, and all
other ICs should be configured to have the SYNC pin dis-
abled with MFR_CONFIG_ALL[4] = 1.
The ASEL_nn pin settings are described in Table 4.
ASEL_ nn selects the subordinate address for the
LTM4683 internal controller. For more details, see Table 5.
NOTE: Per the PMBus specification, pin-programmed
parameters can be overridden by commands from the
digital interface, with the exception of ASEL_nn, which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses, and all parts
will respond to them.
Table 1. VOUTn_CFG Pin Strapping Look-Up Table for the
LTM4683's Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k
R * V
VOUTn_CFG
(kΩ) SETTING COARSE
Open
32.4
0.787
0
*R value indicated is nominal. Select R
VOUTn_CFG
vendor such that its value is always within 3% of the value indicated in the table.
Consider resistor initial tolerance, T .C.R. and resistor operating temperatures,
soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal
shock/cycling, moisture (humidity), and other effects (depending on one's
specific application) could also affect R
effects must be considered in order for resistor pin strapping to yield the
expected result at every SV power-up and/or every execution of MFR_RESET
IN
or RESTORE_USER_ALL, over the lifetime of one's product. R
external to the part. Example:
V
DD25_nn
R
14.3k
(V) MFR_PWM_
OUTn
MODEn[1] BIT
NVM NVM
NVM NVM
0.7 1
0.5 1
from a resistor
VOUTn_CFG
's value over time. All such
VOUTn_CFG
= 14.3k is
TOP
TOP
V _CFG
OUTn
R _CFG
VOUTn
SGND_
nn
For more information
Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the
LTM4683's Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k
R * V
VTRIMn_CFG TRIM
(kΩ)
Open
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
*R value indicated is nominal. Select R
VTRIMn_CFG
resistor vendor such that its value is always within 3% of the value
indicated in the table. Consider resistor initial tolerance, T.C.R. and resistor
operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock/cycling, moisture (humidity), and
other effects (depending on one's specific application) could also affect
R 's value over time. All such effects must be considered in
VTRIMn_CFG
order for resistor pin strapping to yield the expected result at every SV
power-up and/or every execution of MFR_RESET, or RESTORE_USER_ALL
over the lifetime of one's product. R
Example:
V _
nn
DD25
14.3k
V
TRIMn
R
TRIM
SGND_
www.analog.com
LTM4683
(mV) FINE ADJUSTMENT TO V
OUTn
SETTING WHEN RESPECTIVE
0
99
86.625
74.25
61.875
49.5
37.125
24.75
12.375
–12.375
–24.75
–37.125
–49.5
–61.875
–74.25
–86.625
–99
from a
VTRIMn_CFG
= 14.3k is external to the part.
TOP
_CFG
_CFG BOT
nn
35
IN_nn
Rev. 0