Pin Assignment of XADC Connectors
XADC
Connectors
1,2
5,6
9,10
12. Buttons
There are 2 user buttons KEY1~KEY2 on expansion boar, all connected to
normal IOs of FPGA. When press down the buttons, will input low voltage to IOs of
FPGA. When no press down the buttons, will input high voltage to IOs of FPGA. The
buttons circuit schematic as below Figure3-12-1
Http://www.heijin.org
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Figure 3-11-3 XADC on expansion board
FPGA
Input
PIN
magnitude
VP_0 :
Peak-to-Peak
L10
1V
VN_0 :
M9
AD9P :
Peak-to-Peak
J15
1V
AD9N :
H15
AD0P :
Peak-to-Peak
H13
1V
AD0N :
G13
AX7103 User Manual
Description
FPGA
dedicated
XADC
input
channel
FPGA assisted
XADC
input
channel
9
(could use as
normal IO)
FPGA assisted
XADC
input
channel
0
(could use as
normal IO)
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4
7
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