Table of Contents
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J11 Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Figure 3-9-3 below shows the circuit schematic of expansion header (J13).
Http://www.heijin.org
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FPGA PIN
GND
P16
R16
N17
U16
U17
P19
V18
U20
AA9
AA10
W10
Y12
W12
AA15
Y16
AB16
W14
GND
+3.3V
AX7103 User Manual
J11 Pin
FPGA PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+5V
R17
P15
P17
T16
U18
R19
V19
V20
AB10
AA11
V10
Y11
W11
AB15
AA16
AB17
Y14
GND
+3.3V
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4
3
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