Alinx AX7103 FPGA User Manual page 23

PIN37 B13_L8_P
PIN39 GND
PIN41 B14_L11_N
PIN43 B14_L11_P
PIN45 B14_L14_N
PIN47 B14_L14_P
PIN49 GND
PIN51 B14_L5_N
PIN53 B14_L5_P
PIN55 B14_L18_N
PIN57 B14_L18_P
PIN59 GND
PIN61 B13_L17_P
PIN63 B13_L17_N
PIN65 B14_L21_N
PIN67 B14_L21_P
PIN69 GND
PIN71 B14_L22_P
PIN73 B14_L22_N
PIN75 B14_L24_N
PIN77 B14_L24_P
PIN79 B14_IO0
Figure 2-10-2 is the CON2 connector on core board, and the pin1 of connector is
marked on the board.
Connector CON3
The 80-Pin connector CON3 is used to extend the IOs of FPGA bank15 and
bank16, the voltage level of these IOs are +3.3V standard by default, but it can be
changed to other voltage level if we change the VCCO power supply of bank15 and
bank16 by replacing the LDO chipset. Three JTAG signals also connected to CON3
connector for expansion board to access the JTAG interface. The pin assignment of
the CON3 connector is shown in table 2-10-3.
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AA9 3.3V
- Ground
V20 3.3V
U20 3.3V
V19 3.3V
V18 3.3V
- Ground
R19 3.3V
P19 3.3V
U18 3.3V
U17 3.3V
- Ground
T16 3.3V
U16 3.3V
P17 3.3V
N17 3.3V
- Ground
P15 3.3V
R16 3.3V
R17 3.3V
P16 3.3V
P20 3.3V
Figure 2-10-2 CON2 Connector Onboard
2-10-3 Table：Pin Assignment of CON3 Connector
PIN38 B14_L7_P
PIN40 GND
PIN42 B14_L4_P
PIN44 B14_L4_N
PIN46 B14_L9_P
PIN48 B14_L9_N
PIN50 GND
PIN52 B14_L12_N
PIN54 B14_L12_P
PIN56 B14_L13_N
PIN58 B14_L13_P
PIN60 GND
PIN62 B14_L3_N
PIN64 B14_L3_P
PIN66 B14_L20_N
PIN68 B14_L20_P
PIN70 GND
PIN72 B14_L19_N
PIN74 B14_L19_P
PIN76 B14_L23_P
PIN78 B14_L23_N
PIN80 B14_IO25
AX7103 User Manual
W21 3.3V
- Ground
T21 3.3V
U21 3.3V
Y21 3.3V
Y22 3.3V
- Ground
W20 3.3V
W19 3.3V
Y19 3.3V
Y18 3.3V
- Ground
V22 3.3V
U22 3.3V
T18 3.3V
R18 3.3V
- Ground
R14 3.3V
P14 3.3V
N13 3.3V
N14 3.3V
N15 3.3V
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