Alinx AX7103 FPGA User Manual page 13

MT41K256M16HA-125. The DDR3 memory system connected to the memory
connector of BANK 34 and BANK 35 in FPGA. Detail information of DDR3
SDRAM is shown in table 2-4-1 below
Table 2-4-1 DDR3 SDRAM Configuration
Part
U5,U6
The hardware design of DDR3, considered the signal integrity strictly. During
hardware circuit and PCB designation, we consider the register match/ terminal
register/, control the line impedance and length, that all to make sure DDR work high
speed stable.
Connection between FPGA and DDR3 are shown in Figure2-4-1
FPGA
Figure 2-4-2 is DDR3 DRAM on board.
Http://www.heijin.org
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P/N
MT41J256M16HA-125
U1
BANK
34/35
Figure 2-4-1 DDR3 DRAM Schematic
Capacity
256M x 16bit
Data[31:16]
Addr/control
Data[15:0]
AX7103 User Manual
Vender
micron
U5
DDR3
(MT41J256M16
HA)
U6
DDR3
(MT41J256M16
HA)
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