Xilinx IBERT ML628 Getting Started Manual page 38

Creating the GTH IBERT Core
5.
X-Ref Target - Figure 1-38
6.
7.
38
Next in the Project Options window, click on Generation and select the parameters
listed here:
• Design Entry: Verilog
• Vendor: Other
• Netlist Bus Format: B<n:m>
• Preferred Simulation Model: Structural
• ASY Symbol File: unchecked
Figure 1-38 shows the correct settings.
Figure 1-38: CORE Generator Project Options (Generation Options)
Click OK to close the Project Options window.
In the IP Catalog pane of the CORE Generator window
Debug & Verification →
ChipScope Pro →
IBERT Virtex6 GTH (ChipScope Pro - IBERT) 2.03.a
www.xilinx.com
UG806_c1_38_041411
(Figure 1-39) select:
ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011