Xilinx IBERT ML628 Getting Started Manual page 21

X-Ref Target - Figure 1-22
QUAD_115
QUAD_114
QUAD_113
QUAD_112
All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors.
pad.
X-Ref Target - Figure 1-23
ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Figure 1-22: GTX Quad Locations
Figure 1-23 shows the connector pinout.
B
A
GTX Connector Pad
Figure 1-23: A – GTX Connector Pad. B – GTX Connector Pinout
www.xilinx.com
Running the GTX IBERT Demonstration
QUAD_105
QUAD_104
QUAD_102
QUAD_101
QUAD_100
Figure 1-23
B
QUAD_103
UG806_c1_22_041411
shows the connector
A
GTX
P
N
P N
N P
P N
P
N
P N
P
N
P N
P
N
P N
GTX Connector Pinout
UG806_c1_23_041411
21