Table 7-4: Memr# Timing (68000); Figure 13: Memr# Timing (68000) - Epson SED1352 Technical Manual

Epson Research and Development
Vancouver Design Center
MEMR# Timing
AB[19:1]
MEMCS#
AS#
UDS#/LDS#
INVALID
R/W#
Hi-Z
DTACK#
Hi-Z
DB[15:0]
Symbol
t1
AB[19:1] and MEMCS# valid before AS# falling edge
t2
AB[19:1] and MEMCS# hold from AS# rising edge
t3
AS# falling edge to DTACK# falling edge
t4
AS# rising edge to DTACK# hi-z delay
t5
DTACK# falling edge to DB[15:0] valid
t6
DB[15:0] hold from AS# rising edge
t7
AS# rising edge to DB[15:0] hi-z delay
Where MCLK period = 1/f
Hardware Functional Specification
Issue Date: 99/07/28
VALID
t1
t3

Figure 13: MEMR# Timing (68000)

Table 7-4: MEMR# Timing (68000)

Parameter
, or 2/f , or 4/f depending on which mode the chip is in. (see section 9.2 and 9.3).
OSC OSC OSC
t2
t4
t5
VALID
3V/3.3V
Min Typ Max Min
0 0
0 0
3.5 *
MCLK
+ 20
42
20
54
60
Page 31
Hi-Z
t6
Hi-Z
t7
5V
Typ Max Units
ns
ns
3.5 *
MCLK ns
+ 10
20 ns
20 ns
28 ns
30 ns
SED1352
X16-SP-001-16