Implementation; 8-Bit Display Memory Interface; Configuration Options - Epson SED1352 Technical Manual

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3 IMPLEMENTATION

3.1 8-Bit Display Memory Interface

Since 35.7K bytes with at least 116ns access time SRAM is required, one 8K bytes SRAM with 100ns access time, and one
32K bytes SRAM with 100ns access time are used in this example.
12MHz

3.1.1 Configuration Options

VD0 selects 16/8-bit Bus interface. When using a 8-bit memory interface, the 8-bit Bus interface must also be selected. The
state of VD0 is internally latched during RESET. In this example VD0 has no external pull-up resistor and is therefore
latched as a '0' during RESET (due to the internal pull-down resistors) thus selecting the 8-bit Bus interface.
Other option settings are not related to this implementation.
SED1352
X16-AN-005-07
640x240 Panel
VD0-7
VA0-14
VCS0#
VCS1#
OSC1
VOE#
VWE#
SED1352
Figure 1: 8-Bit Memory Configuration Example
Epson Research and Development
Vancouver Design Center
SRM20256-10
D0-7
A0-14
CS
32KB
OE
WE
D0-7
A0-12
CS1
8KB
OE
WE
V
CC
CS2
SRM2264-10
LCD Panel Options / Memory Requirements
Issue Date: 98/10/08