Epson SED1352 Technical Manual page 22

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SED1352
Clock Inputs
Pin Name Type F0B Pin #
OSC1 I 92
OSC2 O 93
Power Supply
Pin Name Type F0B Pin #
V P 3, 53
DD
V P 2, 52
SS
SUMMARY OF CONFIGURATION OPTIONS
Pin Name value on this pin at falling edge of RESET is used to configure:
1
VD0 16-bit host bus interface
VD1 Use direct-mapping for I/O accesses
VD2 MC68000 MPU interface
Swap of high and low data bytes in 16-bit bus
VD3
interface
Select I/O mapping address bits [1:9].
These nine bits are latched on power-up and are compared to the MPU address bits [1-9]. A
valid I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore,
both types of I/O mapping are limited to even address boundaries to determine either the
VD4-VD12
absolute or indexed I/O address of the first register. Note that a "valid I/O cycle" includes
IOCS# being toggled low.
In direct mapping, the base I/O address is selected by VD7-VD12. In indexing, the base I/O
address is selected by VD4-VD12.
Select memory mapping address bits [1:3].
These three bits are latched on power-up and are compared to the MPU address bits [17-19]. A
valid memory cycle combined with a valid address will enable the internal memory decoder.
As only the three most significant bits of the address are compared, the maximum amount of
VD13-VD15
memory supported is 128K bytes. Note that a "valid memory cycle" includes MEMCS# being
toggled low.
If 128K byte memory is used, it must be mapped at an even address so all 128K bytes is
available without a change in state on A17, as this would invalidate the internal compare logic.
16
F1B Pin #
D0B Pad Description
#
This pin, along with OSC2 is the 2-terminal crystal interface when using a
89 2-terminal crystal as the clock input. If an external oscillator is used as a clock
source, then this pin is the clock input.
This pin, along with OSC1 is the 2-terminal crystal interface when using a
90 2-terminal crystal as the clock input. If an external oscillator is used as a clock
source, then this pin should be left unconnected.
F1B Pin #
Description
D0B Pad #
50, 100 Voltage supply.
49, 99 Voltage ground.
0
8-bit host bus interface
Use internal index register for I/O accesses
MPU / Bus interface with memory accesses
controlled by a READY (WAIT#) signal
No byte swap of high and low data bytes in
16-bit bus interface
(1/0)
X16B-C-001-06