Table 7-8: Memr# Timing (Non-68000); Figure 17: Memr# Timing (Non-68000) - Epson SED1352 Technical Manual

Epson Research and Development
Vancouver Design Center
MEMR# Timing
AB[19:0]
BHE#
MEMCS#
MEMR#
READY
DB[15:0]
Symbol
AB[19:0], BHE# and MEMCS# valid before MEMR#
t1
falling edge
AB[19:0], BHE# and MEMCS# hold from MEMR# rising
t2
edge
t3
MEMR# falling edge to READY falling edge
t4
READY rising edge to DB[15:0] valid
t5
DB[15:0] hold from MEMR# rising edge
t6
MEMR# rising edge to DB[15:0] hi-z delay
t7
READY negated pulse width
Where MCLK period = 1/f
Hardware Functional Specification
Issue Date: 99/07/28
VALID
t1
t3 t7
Hi-Z
Hi-Z

Figure 17: MEMR# Timing (Non-68000)

Table 7-8: MEMR# Timing (Non-68000)

Parameter
, or 2/f , or 4/f depending on which mode the chip is in. (see section 9.2 and 9.3)
OSC OSC OSC
t2
Hi-Z
VALID
t4
3V/3.3V
Min Typ Max Min Typ
0
0
30
15
30
30
3.5*
MCLK
+ 30
Page 35
t6
t5
Hi-Z
5V
Max Units
0 ns
0 ns
20 ns
10 ns
28 ns
30 ns
3.5*
MCLK ns
+ 10
SED1352
X16-SP-001-16