Epson SED1352 Technical Manual page 195

Epson Research and Development
Vancouver Design Center
LCD Signal Connector Pinout
SED1352
Pin Name
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
N/C
XSCL
NC
LP
YD
GRND
N/C
VLCD
VCC
+12V
VDDH
WF
LCDENB
SDU1352B0C Rev. 1.0 Evaluation Board User Manual
Issue Date: 98/10/07
Table 1-4: LCD Signal Connector J1 Pinout
LCD
Connector Mono STN LCD
Pin No.
8-bit
1 LD0
3 LD1
5 LD2
7 LD3
9 UD0
11 UD1
13 UD2
15 UD3
17-31
(odd pins)
33 XSCL
35
37 LP
39 YD
2-26
GRND
(even pins)
28
30 VLCD
32 +5V
34 +12V
36 VDDH
38 WF
40 /LCDPWR /LCDPWR LCD power control to external supply
4-bit
Lower panel display data for dual panel-dual drive
mode. In 8-bit single panel-single drive mode, these
are the least significant 4 bits of the 8-bit output data
to the panel (data[3:0]). In 4-bit single panel mode,
these outputs are low.
UD0 Upper panel display data for dual panel-dual drive
mode. In 8-bit single panel-single drive mode, these
UD1
are the most significant 4 bits of the 8-bit output data
UD2
to the panel (data[7:4]). In 4-bit single panel mode,
UD3
these are the 4 data bits output to the panel.
XSCL Shift Clock for LCD data
LP Latch Pulse output
YD Vertical Scanning Start Pulse
GRND Logic Ground
VLCD Negative power supply output (-18V to -23V)
+5V
+12V
VDDH Positive power supply output (+23V to +40V)
WF LCD backplane Bias signal
Comments
X16-AN-002-09
Page 9
SED1352