Epson Research and Development
Vancouver Design Center
3.1.1 MPU with READY (or WAIT#) signal
Z80
MREQ#
IORQ#
A0 to A15
D0 to D7
WAIT#
RESET#
(Maximum mode)
CLK
READY
RESET#
RDY
8284A
Hardware Functional Specification
Issue Date: 99/07/28
A10 to A15
MI#
WR#
RD#
Figure 2: 8-Bit Mode, Example: Z80
(example implementation only - actual may vary)
8086
CLK
S2#
READY
S1#
S0#
RESET#
A16 to A19
A16
BHE#
AD0 to AD15
Figure 3: 16-Bit Mode, Example: i8086 (maximum mode)
(example implementation only - actual may vary)
Decoder
Decoder
8288
CLK
MRDC#
S2#
AMWC#
S1#
IORC#
S0#
AIOWC#
DEN
DT/R
ALE
Decoder
M/IO#
BHE#
A0 to A16
STB
D0 to D15
T
OE
Transceiver
SED1352
MEMCS#
IOCS#
AB0 to AB15
DB0 to DB7
READY
MEMW#
MEMR#
IOR#
IOW#
RESET
SED1352
MEMR#
MEMW#
IOR#
IOW#
AB16 to AB19
AB0 to AB15
BHE#
MEMCS#
IOCS#
DB0 to DB15
RESET
READY
X16-SP-001-16
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SED1352