Memr# Timing; Figure 7-4 Memr# Timing (Mc68000); Table 7-4 Memr# Timing (Mc68000) - Epson S1D13503 Series Technical Manual

EPSON

MEMR# Timing

AB[19:1]
MEMCS#
AS#
UDS#/LDS#
R/W#
DTACK#
DB[15:0]
Symbol
t
AB[19:1] and MEMCS# valid before AS# falling edge
1
t
AB[19:1] and MEMCS# hold from AS# rising edge
2
t
AS# falling edge to DTACK# falling edge
3
t
AS# rising edge to DTACK# hi-z delay
4
t
DTACK# falling edge to DB[15:0] valid
5
t
DB[15:0] hold from AS# rising edge
6
t
AS# rising edge to DB[15:0] hi-z delay
7
Where MCLK = 1/f
Section 9.2 and 9.3.)
1-20
t
1
Hi-Z
t
3
Hi-Z

Figure 7-4 MEMR# Timing (MC68000)

Table 7-4 MEMR# Timing (MC68000)

Parameter
, or 2/f , or 4/f
OSC OSC OSC
VALID
t
5
VALID
3V/3.3V
Min.
0
0
–
–
–
–
–
depending on which display mode the chip is in. (See
t
2
t
4
Hi-Z
t
6
Hi-Z
t
7
5V
Max. Min. Max.
– 0 –
– 0 –
3.5 ∗ 3.5 ∗
–
MCLK MCLK
+ 20 + 10
40 – 15
20 – 15
25 – 15
40 – 30
S18A-A-011-01
Units
ns
ns
ns
ns
ns
ns
ns