Epson SED1352 Technical Manual page 80

Page 50
AUX[05h] Total Display Line Count Register (MSB) and WF Count Register
I/O address = 0101b, Read/Write
WF Count WF Count
Bit 5 Bit 4
bits 7-2 WF Count Bits [5:0]
These bits are used to adjust the WF output signal period. The binary value stored in these bits represents
the number of LP pulses -1 between toggles of the WF output. The power up reset value of these bits is 0,
which causes the WF output to toggle every frame. When values of 01h to 3Fh are programmed into these
bits, the results are WF toggling every 1+n LP pulses, where n is the value programmed.
bits 1-0 Total Display Line Count Bits [9:8]
These are the two MSB of the Total Display Line Count Register, AUX[04h].
AUX[06h] Screen 1 Display Start Address Register (LSB)
I/O address = 0110b, Read/Write.
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 7 Bit 6
AUX[07h] Screen 1 Display Start Address Register (MSB)
I/O address = 0111b, Read/Write.
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 15 Bit 14
AUX[06h] bits 7-0 Screen 1 Display Start Address Bits [15:0]
AUX[07h] bits 7-0 These 16 bits determine the Screen 1 Display Start Address. In an 8-bit memory configuration these bits
set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most sig-
nificant bits of a 17-bit start address (i.e., word access).
The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel (top
left corner). In a dual panel configuration, screen 1 refers to the upper half of the display. While in a single
panel configuration, screen 1 refers to the first screen of the Split Screen Display feature where two differ-
ent images (screen 1 and screen 2) can be displayed at the same time on one display.
Note
The absolute address into display memory is determined by the Memory Mapping
Address which is set by VD13 - VD15 (see Table 5-6, "Summary of Power On / Re-
set Options," on page 25).
SED1352
X16-SP-001-16
WF Count WF Count
Bit 3 Bit 2
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 5 Bit 4
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 13 Bit 12
WF Count WF Count
Bit 1 Bit 0
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 3 Bit 2
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 11 Bit 10
Epson Research and Development
Vancouver Design Center
Total Total
Display Display
Line Count Line Count
Bit 9 Bit 8
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 1 Bit 0
Screen 1 Screen 1
Display Display
Start Addr Start Addr
Bit 9 Bit 8
Hardware Functional Specification
Issue Date: 99/07/28