Pin Assignment - Balluff MATRIX VISION mvBlueNAOS Technical Manual

40

1.9.3.1 Pin assignment

Note
The red dot marks pin 1 of Hirose DF40GB(3.0)-70DS-0.4V.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Signal Description
VCC_IN Input Voltage (5V-12V)
VCC3V3 Power Output, max. 10mA for customer use
VCC_IN Input Voltage (5V-12V)
I2C_SCL_USER I2C_USER (see details below)
LVCMOS 3.3V IO level
VCC_IN Input Voltage (5V-12V)
I2C_SDA_USER I2C_USER (see details below)
LVCMOS 3.3V IO level
DigIn0 Digital input (with level shifter)
Voltage reference VCC_IO
UART_RX LVCMOS 3.3V IO level
100 Ohm series resistor placed on mainboard
DigIn1 Digital input (with level shifter)
Voltage reference VCC_IO
UART_TX LVCMOS 3.3V IO level
100 Ohm series resistor placed on mainboard
GND Ground
GND Ground
GND Ground
GND Ground
PCIe_CLK_P PCIE_CLK + (differential)
- Do not connect, internal use
PCIe_CLK_N PCIE_CLK - (differential)
- Do not connect, internal use
GND Ground
GND Ground
PCIe_TX0_P PCIe Transmitter (differential)
- Do not connect, internal use
PCIe_TX0_N PCIe Transmitter (differential)
- Do not connect, internal use
GND Ground
GND Ground
GND Ground
GND Ground
DigIn2 Digital input (with level shifter)
Voltage reference VCC_IO
GND Ground
DigIn3 Digital input (with level shifter)
Voltage reference VCC_IO
PCIe_RX3_P PCIe Receiver (differential)
GND Ground
PCIe_RX3_N PCIe Receiver (differential)
PCIe_TX1_P PCIe Transmitter (differential)
GND Ground
PCIe_TX1_N PCIe Transmitter (differential)
PCIe_RX0_P PCIe Receiver (differential)
MATRIX VISION GmbH