Epson S1D13503 Technical Manual page 185

S1D13503F00A Register Summary S1D13503F00A Register Summary
AUX[00] T EST R EGISTER : I/O address = 0000b, RW
Test Input Select / Scratch
Test Mode reserved
Enable must = 0
Bit 2 Bit 1
AUX[01] M ODE R EGISTER 0: I/O address = 0001b, RW
Gray Shade
DISP Panel Mask XSCL LCDE
/ Color
AUX[02] L B C R (LSB): I/O address = 0010b, RW
INE YTE OUNT EGISTER
Line Byte Count (low byte)
Bit 7 Bit 6 Bit 5 Bit 4
AUX[03] M ODE R EGISTER 1: I/O address = 0011b, RW
Power Save Mode
LCD Signal LCD Data
LUT Bypass
State Width Bit 1
Bit 1 Bit 0
AUX[04] T OTAL D ISPLAY L INE C OUNT R EGISTER (LSB): I/O address = 0100b, RW
Total Display Line Count (low byte)
Bit 7 Bit 6 Bit 5 Bit 4
AUX[05] T D L C R (MSB)
OTAL ISPLAY INE OUNT EGISTER AND
WF Count
Bit 5 Bit 4 Bit 3 Bit 2
AUX[06] S 1 D S A R (LSB):
CREEN ISPLAY TART DDRESS EGISTER
Screen 1 Display Start Address (low byte)
Bit 7 Bit 6 Bit 5 Bit 4
AUX[07] S 1 D S A R (MSB):
CREEN ISPLAY TART DDRESS EGISTER
Screen 1 Display Start Address (high byte)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
AUX[08] S 2 D S A R (LSB):
CREEN ISPLAY TART DDRESS EGISTER
Screen 2 Display Start Address (low byte)
Bit 7 Bit 6 Bit 5 Bit 4
AUX[09] S CREEN 2 D ISPLAY S TART A DDRESS R EGISTER (MSB):
Screen 2 Display Start Address (high byte)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
AUX[0A] S 1 D L C R (LSB):
CREEN ISPLAY INE OUNT EGISTER
Screen 1 Display Line Count (low byte)
Bit 7 Bit 6 Bit 5 Bit 4
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AUX[0B] S
Test Output Select / Scratch
1
n/a
Bit 0 Bit 2 Bit 1 Bit 0
AUX[0C] H
LCD Data Memory
RAMS
Width Bit 0 Interface
Bit 7
AUX[0D] A
Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
AUX[0E] L
OOK
BW / 256 Line Byte
Green Bank Select
Color Mode
Colors Count Bit 8
Bit 1
AUX[0F] L
OOKUP
Red Bank Select
Bit 3 Bit 2 Bit 1 Bit 0
Bit 1
WF C R : I/O address = 0101b, RW
OUNT EGISTER
Total Display Line Count Notes
Bit 1 Bit 0 Bit 9 Bit 8 1 n/a bits should be written 0.
2 These bits are used to identify the S1D13503 at power on / RESET. If these bits read 00b at Power On /
Reset the device is an S1D13503F00A. If this bit reads 10b at Power On / Reset the device is an
I/O address = 0110b, RW
S1D13502F00B. If this bit reads 11b at Power On / Reset the device is an S1D13502F00A.
Bit 3 Bit 2 Bit 1 Bit 0
I/O address = 0111b, RW
Bit 10 Bit 9 Bit 8
I/O address = 1000b, RW
Bit 3 Bit 2 Bit 1 Bit 0
I/O address = 1001b, RW
Bit 10 Bit 9 Bit 8
I/O address = 1010b, RW
Bit 3 Bit 2 Bit 1 Bit 0
CREEN 1 D ISPLAY L INE C OUNT R EGISTER (MSB): I/O address = 1011b, RW
n/a n/a n/a n/a n/a
ORIZONTAL N ON -D ISPLAY P ERIOD R EGISTER : I/O address = 1100b, RW
Horizontal Non-Display period
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
P A R : I/O address = 1101b, RW
DDRESS ITCH DJUSTMENT EGISTER
Address Pitch Adjustment
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
-U T A R : I/O address = 1110b, RW
P ABLE DDRESS EGISTER
2
ID / RGB Index Palette Address
Bit 0 Bit 1 Bit 0 Bit 3 Bit 2
T D R : I/O address = 1111b, RW
ABLE ATA EGISTER
Blue Bank Select Palette Data
Bit 0 Bit 1 Bit 0 Bit 3 Bit 2
Screen 1 Disp Line Count
Bit 9 Bit 8
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
X18A-Q-002-05
01/03/02