Power Save Modes; Power Save Mode 1; Power Save Mode 2; Table 8-9: Power Save Mode Selection - Epson S1D13503 Technical Manual

Epson Research and Development
Vancouver Design Center

8.3 Power Save Modes

Two software-controlled Power Save Modes have been incorporated into the S1D13503 to accommodate the important
need for power reduction in the hand-held devices market. These modes can be enabled by setting the two Power Save bits
(AUX[03] bits 7:6).
The various settings are:
Bit 5 Bit 4
0
0
1
1

8.3.1 Power Save Mode 1

Power Save Mode 1 has two states. Initially when set, the S1D13503 enters State 1. If no valid memory cycle is detected
within 1, 2, or 4 clocks (input clock frequency dependent), the chip will enter State 2. The number of clocks of inactivity
before entering State 2 is dependent on the display memory interface and the number of Gray shades.
State 1
• I/O read/write of all registers allowed
• Memory read/write allowed
• LCD outputs are either forced low (AUX[03] bit 5=0), or high impedance (AUX[03] bit 5=1)
State 2
The same as State 1 as well as:
• Master clock for display memory access is disabled
Once a valid memory read/write cycle is detected, the S1D13503 returns to State 1 where the MPU access is serviced. The
transition from going from State 2 to State 1 requires 1, 2, or 4 clocks (as described above).

8.3.2 Power Save Mode 2

• I/O read/write of all registers allowed
• Memory read/write is disabled
• Master clock for display memory access is disabled
• LCD outputs are either forced low (AUX[03] bit 5=0), or high impedance (AUX[03] bit 5=1)
• Internal oscillator is disabled.
Hardware Functional Specification
Issue Date: 01/01/29
Downloaded from Elcodis.com electronic components distributor

Table 8-9: Power Save Mode Selection

Mode Activated
0 Normal Operation
1 Power Save Mode 1
0 Power Save Mode 2
1 Reserved
Page 77
S1D13503
X18A-A-001-08