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Page 10
2 FEATURES
2.1 Technology
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low power CMOS
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2.7 to 5.5 volt operation
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100 pin QFP5-S2 surface mount package
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100 pin QFP15-STD surface mount package
2.2 System
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maximum 25 MHz input clock (or pixel clock)
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2-terminal crystal input for internal oscillator or direct connection to external clock source
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maximum 16 MHz, 16-bit MC68000 MPU interface
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8-bit or 16-bit MPU/Bus interface with memory accesses controlled by a READY (or WAIT#) signal
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option to use built-in index register or direct-mapping to access one of sixteen internal registers
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8-bit or 16-bit SRAM data bus interface configurations
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display memory configurations :
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128k bytes using one 64Kx16 SRAM
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128k bytes using two 64Kx8 SRAMs
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64k bytes using two 32Kx8 SRAMs
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40k bytes using one 8Kx8 and one 32Kx8 SRAM
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32k bytes using one 32Kx8 SRAM
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16k bytes using two 8Kx8 SRAMs
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8k bytes using one 8Kx8 SRAM
2.3 Display Modes
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1 bit-per-pixel, black-and-white display mode
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2/4 bits-per-pixel, 4/16 level gray shade display modes
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2/4/8 bits-per-pixel, 4/16/256 level color display modes
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one 16x4 Look-Up Table provided for gray shade display modes
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three 16x4 Look-Up Tables provided for color display modes
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maximum 16 shades of gray
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maximum 256 simultaneous colors from a possible 4096 colors
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split screen display mode (see AUX[0A])
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virtual display mode (see AUX[0D])
Note
256 color display mode support requires a 16-bit display memory interface
S1D13503
X18A-A-001-08
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Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/01/29
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