Epson S1D13503 Technical Manual page 76

Page 68
AUX[0A] Screen 1 Display Line Count Register (LSB)
I/O address = 1010b, Read/Write.
Screen 1 Screen 1
Display Display
Line Count Line Count
Bit 7 Bit 6
AUX[0B] Screen 1 Display Line Count Register (MSB)
I/O address = 1011b, Read/Write.
n/a n/a
AUX[0A] bits 7-0 Screen 1 Display Line Count Bits [9:0]
AUX[0B] bits 1-0 These bits are the eight LSB of a 10-bit value used to determine the number of lines displayed for screen 1.
S1D13503
X18A-A-001-08
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Screen 1 Screen 1
Display Display
Line Count Line Count
Bit 5 Bit 4
n/a n/a
The remaining lines will automatically display from the screen 2 display start address. The 10-bit value
programmed is the number of display lines -1.
This register is used to enable the split screen display feature (single panel only) where two different
images can be displayed at the same time on one display.
For example; AUX[0A] = 20h for a 320x240 display system. The display will display 20h+1 = 33 lines on
the upper part of the screen as dictated by the screen 1 display start address registers (AUX[06] and
AUX[07]), and 240 - 33 = 207 lines will be displayed on the lower part of the screen as dictated by the
screen 2 display start address registers (AUX[08] and AUX[09]).
Two different images can be displayed when using a dual panel configuration by changing the screen 2 dis-
play start address. However, by using this method screen 2 is limited to the lower half of the display.
This register is ignored in dual panel mode.
Screen 1 Screen 1 Screen 1
Display Display Display
Line Count Line Count Line Count
Bit 3 Bit 2 Bit 1
Screen 1
Display
n/a n/a
Line Count
Bit 9
Epson Research and Development
Vancouver Design Center
Screen 1
Display
Line Count
Bit 0
Screen 1
Display
Line Count
Bit 8
Hardware Functional Specification
Issue Date: 01/01/29