Epson S1D13503 Technical Manual page 107

Epson Research and Development
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AUX
Register
AUX[05h] 0000 0000
AUX[06h]
AUX[07h]
AUX[08h]
AUX[09h]
AUX[0Ah] 1110 1111
AUX[0Bh] 0000 0000
AUX[0Ch] 0000 0000
AUX[0Dh] 0000 0000
AUX[0Eh] 0000 0000
AUX[0Fh] 0000 0000
AUX[0Fh] 0000 0000 write Green data
AUX[0Fh] 0000 0000 write Blue data
AUX[0Eh] 0000 0001 increment palette address
AUX[0Fh] 0000 0010 write Red data
AUX[0Fh] 0000 0010 write Green data
AUX[0Fh] 0000 0101 write Blue data
AUX[0Eh] 0000 0010 increment palette address
Programming Notes and Examples
Issue Date: 01/01/30
Downloaded from Elcodis.com electronic components distributor
Data
(in Binary)
• bits 7-2: 0 = WF output toggles every frame (panel specific)
• bits 1-0 = bits 9-8 of Total Display Line Count (panel specific,
see AUX[04h])
• bits 15-0 of Screen 1 Display Start Address - normally Screen 1
Start Address = 0000h (application and panel specific)
0000 0000
bits 7-0 are in AUX[06h] and bits 15-8 are in AUX[07h]
0000 0000
when 0000h, Screen 1 Display Start Address is located at
D000:0000h, bank 0, on the S5U13503B00C
• bits 15-0 of Screen 2 Display Start Address - normally Screen 2
Start Address = 0000h (application and panel specific)
0000 0000
bits 7-0 are in AUX[08h] and bits 15-8 are in AUX[09h]
0000 0000
when 0000h, Screen 1 Display Start Address is located at
D000:0000h, bank 0, on the S5U13503B00C
• bits 7-0 = bits 7-0 of Screen 1 Display Line Count
bits 9-8 of Screen 1 Display Line Count in bits 1-0 of AUX[0Bh]
Screen 1 Display Line Count is typically the same as Total Display
Line Count (AUX[0Ah] = AUX[04h], bits 1-0 of AUX[0Bh] = bits
1-0 of AUX[05h])
• bits 7-2 = don't care; recommend clearing bits
• bits 1-0 = bits 9-8 of Screen 1 Display Line Count (application
specific, see AUX[0Ah])
normally programmed to 00h (panel specific)
• bits 7-0 = use fixed default non-display period
normally programmed to 00h (normal)
• bits 7-0 = no address pitch adjustment when 0
select palette address
• bits 7-6 = green bank 0 (application specific)
• bits 5-4 = auto increment palette R/W access (application
specific)
• bits 3-0 = palette address (application specific)
write Red data
• bits 7-6 = red bank 0 (application specific)
• bits 5-4 = blue bank 0 (application specific)
• bits 3-0 = palette data (application specific)
Notes
Page 11
See Also
see Section 4.2.1,
"S5U13503B00C
Evaluation Board
Display Memory" on
page 36 and Section 4.1,
"Registers" on page 34
see Section 4.2.1,
"S5U13503B00C
Evaluation Board
Display Memory" on
page 36 and Section 4.1,
"Registers" on page 34
see Section 5.4, "Split
Screen" on page 45
see Section 5.1, "Virtual
Displays" on page 40
S1D13503
X18A-G-002-06