Mitsubishi MELSEC L Series User Manual page 353

Special
ACPU Special
Register
Special Register for
after
Register Modification
Conversion
D9116 SD1116
D9117 SD1117
D9118 SD1118
D9119 SD1119
D9120 SD1120
D9121 SD1121
D9122 SD1122
D9123 SD1123
D9124 SD1124 SD63
D9125 SD1125 SD64
D9126 SD1126 SD65
D9127 SD1127 SD66
D9128 SD1128 SD67
D9129 SD1129 SD68
D9130 SD1130 SD69
D9131 SD1131 SD70
D9132 SD1132 SD71
*1 The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU
Name Meaning
Bit pattern, in
units of 16
I/O module points,
- verification indicating the
error modules with
verification
errors
Number of Number of
annuciator annuciator
detections detections
Annunciator Annunciator
detection detection
number number
Details
• If the status of the I/O module changes from that obtained
at power-on, the module No. (unit: 16 points) is stored in
the following bit pattern. (When I/O module numbers have
been set by the parameter, the parameter-set numbers are
stored.)
b15 b14b13b12b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 0
SD1116
1
0 0 0 0 0 0 XY 0 0
SD1117
190
1
0 0 0 0 0 0 0 0
SD1123 XY
7B0
Indicates an I/O module verify error
For a module whose number of I/O points exceeds 16
points, all bits corresponding to I/O module numbers within
the number of I/O points occupied by the module (in
increments of 16 points) turn on.
Ex.
When a 64-point module is mounted on the slot 0, b0
to b3 turn on when an error is detected.
• I/O module verification is conducted on I/O modules on
remote I/O stations.
(If normal status is restored, clear is not performed.
Therefore, it is required to perform clear by user program.)
When any of F0 to F2047 (default device setting) is turned
on by the SET F instruction, a value in SD1124 is
incremented by one (up to a maximum of 16). When the RST
F or LEDR instruction is executed, it is decremented by one.
When any of F0 to F2047 (default device setting) are turned
on by the SET F instruction, the annunciator numbers (F
numbers) that are turned on are stored in SD1125 to SD1132
in order.
The F numbers turned off by the RST F instruction is deleted
from this register, and the F numbers stored after the deleted
F numbers are shifted to the previous registers. When the
LEDR instruction is executed, the contents of SD1125 to
SD1132 are shifted upward by 1.
When there are eight annunciator detections, the next one is
not stored in SD1125 to SD1132.
SET SET SET RST SET SET SET SET
F50 F25 F99 F25 F15 F70 F65 F38
0 50 50 50 50 50 50 50 50 50 50 50 99
SD1009
0 1 2 3 2 3 4
SD1124
0 50 50 50 50 50 50 50 50 50 50 50 99
SD1125
0 0 25 25 99 99 99 99 99 99 99 99 15
SD1126
0 0 0 99 0 15 15 15 15 15 15 15 70
SD1127
0 0 0 0 0 0 70 70 70 70 70 70 65
SD1128
0 0 0 0 0 0
0 65 65 65 65 65 38
SD1129
0 0 0 0 0 0
0
SD1130
0 0 0 0 0 0 0
SD1131
0 0 0 0 0 0 0
SD1132
APPENDICES
Corre-
sponding
CPU
1
0 0 0 0 0 0
XY
0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
Qn(H)
QnPH
*1
QnU
LCPU
SET SET SET
F210 LEDR
F110 F151
5 6 7 8 8 8
0 38 38 38 38 110
0 0 110 110 110 151
0 0 0 151 151 210
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