Mitsubishi MELSEC L Series User Manual page 306

Number Name
Stores the
transmission
Transmission
speed specified
SD100 speed storage
in the serial
area
communication
setting.
Stores the
communication
Communication
setting specified
SD101 setting storage
in the serial
area
communication
setting.
Stores the
transmission
Transmission wait time
SD102 wait time specifed in the
storage area serial
communication
setting.
CH1 Stores a
transmission transmission
SD105
speed setting speed (RS-
(RS-232) 232).
Stores the data
Data sending sending result
SD110 result storage when the serial
area communication
function is used.
Stores the data
Data receiving receiving result
SD111 result storage when the serial
area communication
function is used.
Amount of Amount of
SD118 battery battery
consumption consumption
304
Meaning
This register stores the transmission speed specified in the
serial communication setting parameter.
96 : 9.6kbps,192 : 19.2kbps, 384 : 38.4kbps,
576 : 57.6kbps,1152 : 115.2kbps
This register stores the value indicating the communication
setting specified in the serial communication setting parameter.
b15 to
Since this area is reserved for
a system, storage data are variable.
Write during RUN setting
0: Disabled
1: Enabled
This register stores the transmission wait time specified in the
serial communication setting parameter.
0: No waiting time
10 to 150: Waiting time (unit: ms)
Default: 0
This register stores a transmission speed (When an external
device is not connected, the default is 1152).
Note when the serial communication setting is configured, this
register stores the transmission speed specified in the
parameter.
96 : 9600bps, 192 : 19.2kbps,384 : 38.4kbps,
576 : 57.6kbps, 1152 : 115.2kbps
Stores the error code at the time of sending data.
Stores the error code at the time of receiving data.
This register stores a battery consumption rate.
[Value range]
• 1 or 2: Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU,
Q03UD(E)CPU, Q04UD(E)HCPU, L02CPU,
L02CPU-P
• 1 to 3: Q06UD(E)HCPU, L26CPU-BT, L26CPU-PBT
• 1 to 4: Q10UD(E)HCPU, Q20UD(E)HCPU, Q13UD(E)HCPU,
Q26UD(E)HCPU
• 1 to 5: Q50UDEHCPU, Q100UDEHCPU
Explanation
b6 b5 b4 b3 b0
to
Since this area is
reserved for a system,
storage data are variable.
Sumcheck presence
0: Absent
1: Present
Corre-
Corre-
sponding
Set by
sponding
(When Set) ACPU
D9
S
Q00/Q01
(Power-ON or
QnU
reset)
New
Qn(H)
QnPH
QnPRH
S
QnU
LCPU
Q00/Q01
S
(Error)
QnU
S
(Status
LCPU
change)
CPU
*4
*3
*4
QnU