Mitsubishi MELSEC L Series User Manual page 320

Hide thumbs Also See for MELSEC L Series:
Table of Contents

Advertisement

Number
Name
Number of
SD393
multiple CPUs
CPU mounting
SD394
information
Multiple CPU
system
Multiple CPU
SD395
information
number
No. 1 CPU
SD396
operation
status
No. 2 CPU
SD397
operation
status
No. 3 CPU
SD398
operation
status
No. 4 CPU
SD399
operation statu
*1
Function version is B or later.
*2
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*3
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*4
The module whose first 5 digits of serial No. is "08032" or later.
*5
The module whose first 5 digits of serial No. is "09012" or later.
*6
The module whose first 5 digits of serial No. is "10042" or later.
*7
The Universal model QCPU except the Q00UJCPU.
*8
This applies when the first five digits of the serial number is "12052" or later.
*9
This applies when the first five digits of the serial number is "13072" or later.
318
Meaning
The number of CPU modules that comprise the multiple CPU
system is stored. (1 to 3, Empty also included)
This register stores information on the CPU module types of
CPU No.1 to No.3 and whether or not the CPU modules are
mounted.
b15
b12 b11
to
SD394
Empty (0)
CPU module mounted or
not mounted
0: Not mounted
1: Mounted
In a multiple CPU system configuration, the CPU number of the
host CPU is stored.
CPU No. 1: 1, CPU No. 2: 2, CPU No. 3: 3, CPU No. 4: 4
The operation information of each CPU No. is stored.
(The information on the number of multiple CPUs indicated in
SD393 is stored.)
to
b15
b14
Empty
mounted
0: Not mounted
1: Mounted
Explanation
b8 b7
b4 b3
to
to
to
CPU No.3
CPU No.2
CPU No.1
CPU module type
0: Programmable
controller CPU
1: Motion CPU
2: PC CPU module
4: C Controller
module
to
b8 b7
to
b4 b3
Classification Operation status
0: Normal
0: RUN
1: Minor fault
2: STOP
2: Medium fault
3: PAUSE
3: Major fault
4: Initial
F
: Reset
F
: Reset
H
H
Corre-
sponding
Set by
(When Set)
ACPU
D9
b0
S
(Initial)
New
b0
S
(END
processing
error)
Corre-
sponding
CPU
*1
Q00/Q01
QnU
*1
Q00/Q01
*1
Q00/Q01
*1
Qn(H)
QnPH
QnU
*1
Q00/Q01
QnU
*1
Q00/Q01
*7
QnU
*3
QnU

Advertisement

Table of Contents
loading

Table of Contents