Mitsubishi MELSEC L Series User Manual page 304

Number Name
Bit pattern
indicating
SD52 Battery low where battery
voltage drop
occurred
Number of
AC/DC DOWN times for AC/DC
SD53
detection DOWN
detection
Number of Number of
SD60 module with module with
blown fuse blown fuse
I/O module I/O module
SD61 verify error verify error
number module number
Annunciator Annunciator
SD62
number number
Number of Number of
SD63
annunciators annunciators
SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
SD72
SD73
Table of
SD74
Annunciator
detected
detection
SD75
annunciator
number
numbers
SD76
SD77
SD78
SD79
SD80 CHK number CHK number
302
Meaning
• This register has the same bit pattern as that of SD51.
• After an alarm is detected (the alarm bit turns on), the alarm
bit turns off if an error is detected (the error bit turns on).
(Universal model QCPU only)
• This register stores "0" (turns off) when the battery voltage
returns to normal.
• A value stored in this register is incremented by 1 whenever
the input voltage falls to or below 85% (AC power)/65% (DC
power) of the rating during operation of the CPU module.
• The counter repeats increment and decrement of the value;
0→32767→-32768→0
Value stored here is the lowest station I/O number of the
module with the blown fuse.
The lowest I/O number of the module where the I/O module
verification number took place.
This register stores the number of the annunciator (F number)
detected first.
This register stores the number of detected annunciators.
When an annunciator (F) is turned on by the OUT F or SET F
instruction, the F numbers are stored from SD64 to SD79 in
chronological order.
The number of an annunciator (F) turned off by the RST F
instruction is deleted from SD64 to SD79, and F numbers
stored later than the register where the deleted F number was
stored are shifted upward.
When the LEDR instruction is executed, the contents of SD64
to SD79 are shifted upward by 1. After 16 annunciators have
been detected, detection of the 17th will not be stored from
SD64 through SD79.
SET SET SET
F50 F25 F99
SD62 0 50 50 50 50 50 50 50 50 50 50 50 99 (Number
SD63 0 1 2 3
SD64 0 50 50 50 50 50 50 50 50 50 50 50 99
SD65 0 0 25 25 99 99 99 99 99 99 99 99 15
SD66 0 0 0 99 0 15 15 15 15 15 15 15 70
SD67 0 0 0 0
SD68 0 0 0 0
SD69 0 0 0 0
SD70 0 0 0 0
SD71 0 0 0 0
SD72 0 0 0 0
SD73 0 0 0 0
SD74 0 0 0 0
SD75 0 0 0 0
SD76 0 0 0 0
SD77 0 0 0 0
SD78 0 0 0 0
SD79 0 0 0 0
Error codes detected by the CHK instruction are stored as BCD
code.
Explanation
RST SET SET SET SET SET SET SET
F25 F15 F70 F65 F38 F110 F151 F210 LEDR
detected)
(Number of
2 3 4 5 6 7 8 9 8
annunciators
detected)
0 0 70 70 70 70 70 70 65
0 0 0 65 65 65 65 65 38
0 0 0 0 38 38 38 38 110
0 0 0 0 0 110 110 110 151
0 0 0 0 0 0 151 151 210
0 0 0 0 0 0 0 210 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Corre-
sponding
Set by
(When Set) ACPU
D9
S
D9005
(Error)
D9000
D9002
D9009
D9124
D9125
D9126
D9127
D9128
D9129
D9130
D9131
D9132
S
(Instruction
execution)
(Number
detected)
Corre-
sponding
CPU
New
QCPU
LCPU
QCPU
QCPU
LCPU
New
Qn(H)
QnPH
QnPRH