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10.1.1
CSI D-PHY Design Guidelines
Table 10-6 details the signal routing requirements for CSI D-PHY interface.
Table 10-6.
MIPI CSI D-PHY Interface Signal Routing Requirements
Parameter
Max Data Rate (per data lane)
High-Speed mode
Max Frequency (for Low Power mode)
Number of Loads
Max Loading (per pin)
Reference plane
Breakout Region Impedance (Single Ended)
Max PCB breakout delay
Trace Impedance
Diff pair / Single Ended
Via proximity (Signal to reference)
Trace spacing - Microstrip / Stripline
Max Insertion loss
1 Gbps
1.5 Gbps
2.5 Gbps
Max trace delay / length (Stripline/Microstrip)
1 Gbps
1.5 Gbps
2.5 Gbps
Max Intra-pair Skew
Max Trace Delay Skew between DQ & CLK
1 / 1.5 / 2.5 Gbps
Noise Coupling Avoidance
Notes:
1.
Up to 4 signal vias can share a single GND return via
2.
If routing to device includes a flex or 2nd PCB, the max trace and skew calculations must include all the PCBs/flex routing
Jetson AGX Xavier Series Product
Requirement
2.5
Gbps
10
MHz
1
load
10
pF
GND
45-50
Ω
48
ps
90-100 / 45-50
Ω
< 3.8 (24)
mm (ps)
2x / 2x
dielectric
3.10
dB
2.96
2.17
3000 (435) / 2610 (435)
ps (mm)
2242 (325) / 1953 (325)
1173 (170) / 1018 (170)
1
ps
40/26.7/16
ps
Keep critical traces away from other signal traces or unrelated power
traces/areas or power supply components
Units
Notes
±15%
See Note 1
See Note 2
See Note 2
DG-09840-001_v2.5 | 87
Video Input
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