Table 7-5. Ufs And Miscellaneous Usb Control Pin Descriptions; Table 7-6. Usb 3.1, Pcie And Ufs Lane Mapping Configurations - Nvidia Jetson AGX Xavier Series Design Manual

Pin # Module Pin SoC Signal
Name
H10 PEX_L5_RST_N PEX_L5_RST_N
E31 NVHS0_SLVS_RE NVHS0_REFCLK_
FCLK0_N N
E30 NVHS0_SLVS_RE NVHS0_REFCLK_
FCLK0_P P
E26 UPHY_ PEX_REFCLK1_N UPHY Reference Clock 1. Unused.
REFCLK1_N
E27 UPHY_ PEX_REFCLK1_P
REFCLK1_P
F29 UPHY_ PEX_REFCLK2_N UPHY Reference Clock 2. Unused.
REFCLK2_N
F28 UPHY_ PEX_REFCLK2_P
REFCLK2_P
A8 PEX_WAKE_N PEX_WAKE_N
Notes:
1. In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals.
2. The direction shown in this table for PEX_Lx_RST_N, PEX_Lx_CLKREQ_N and PCIE_WAKE_N signals is true when used for
those PCIe functions. Otherwise if used as GPIOs, the direction is bidirectional.
Table 7-5. UFS and Miscellaneous USB Control Pin Descriptions
Pin # Module Pin Name SoC Signal
A6 UFS0_REF_CLK UFS0_REF_CLK
C6 UFS0_RST_N UFS0_RST
A62 GPIO10 CAN1_WAKE
F54 GPIO22 USB_VBUS_EN0
Table 7-6. USB 3.1, PCIe and UFS Lane Mapping Configurations
Jetson AGX Xavier Lanes
Avail. Outputs from Jetson
AGX Xavier
USB 3.1 PCIe UFS
3 2 x1, 1 x2, 1 1 x1
x4 & 1 x8
Jetson AGX Xavier Series Product
Usage/Description
when Jetson AGX Xavier is Endpoint. Pulled to
3.3V through 47kΩ resistor on-module.
PCIe 5 Reset. Output when Jetson AGX Xavier is
Root Port. Input when Jetson AGX Xavier is
Endpoint. Pulled to 3.3V through 4.7kΩ resistor
on-module.
PCIe/SLVS Reference Clock 0. Unused if
controller #5 (NVHS[7:0] lanes) configured as
Root Port. Receives 100Mhz clock if configured
as Endpoint.
PCIe Wake. Wake signal shared by all PCIe
interfaces. Pulled to 3.3V through 47kΩ resistor
on-module.
Usage/Description
UFS Reference Clock
UFS Reset
GPIO
GPIO
UPHY0 UPHY1 UPHY[5:2
]
PCIe x1 USB 3.1 PCIe x4
(C1) (P2) (C0)
Usage on NVIDIA
Carrier Board
Unused
PCIe x16 Connector and
M.2 Key E and
Connector
Usage on NVIDIA Carrier Board
Micro SD / UFS Card Socket
Micro SD / UFS Card Socket
USB PD Controller Interrupt
VDD_5V_SATA Load Switch
Enable
UPHY6 UPHY7 UPHY[9:8
]
USB 3.1 PCIe x1 PCIe x2
(P0) (C3) (C4)
USB, PCIe, and UFS
Direction Pin Type
Bidir
Input UPHY/SLVS Diff
Pair
Input UPHY Diff Pair
Input Open-Drain –
3.3V
Direction Pin Type
Output CMOS – 1.2V
Output CMOS – 1.2V
Bidir CMOS – 3.3V
Output CMOS – 1.8V
UPHY10 UPHY11 NVHS[7:0
]
UFS x1 USB 3.1 PCIe x8
(0) (P3) (C5)
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