Power Button Supervisor Mcu Power-On; Figure 5-7. Optional Acok Circuitry; Table 5-4. Power Button Supervisor Control Signals - Nvidia Jetson AGX Xavier Series Design Manual

Figure 5-7. Optional ACOK Circuitry
To Module
ACOK_AP_L
VCOMP_ALERT_N
(Pin F61)
Pulled low for
Auto-Power-On
ACOK_L
or connected
to charger
ACOK output
From Powergood 5V_AO_PGD
on 5V_AO Supply
From Module CARRIER_PWR_ON
(Pin L62)
Note: See Figure 5-6.
5.4.2

Power Button Supervisor MCU Power-On

The NVIDIA Jetson AGX Xavier carrier board implements a power button supervisor. This
supervisor is a low power device meant to intercept push-button (momentary) switches to
control ON/Enable signals to the module PMIC and main processor. This supervisor is always
powered and allows close to complete system power OFF while providing proper timing for
ON/OFF signals to the system. The selected MCU to perform this function is the
EFM8SB10F8G-A-QFN20 from Silicon Labs.
Note: Designs that intend to follow the NVIDIA carrier board design and include the
EFM8SB10F8G-A-QFN20 MPU for Button Power Button control need to replicate the circuitry on
the latest P2822 carrier board exactly. NVIDIA will provide the binary and the customer should
get the flashing instructions from Silicon Labs. Otherwise, another solution such as the one
described earlier in the Power-On (No MCU) can be used.
Table 5-4. Power Button Supervisor Control Signals
Signal Name Associated
Module Pin #
BUTTON_POWER_ON*
ACOK
CARRIER_POWER_ON
RESET_N (SYS_RESET_N)
FORCE_SHUTDOWN_N
(OVERTEMP_N)
BRD_SEL
VIN_PWR_ON
MODULE_POWER_ON
POWER_BTN_N
Jetson AGX Xavier Series Product
VDD_1V8
5V_AO_ONKEY
4.75kΩ,1%
5V_AO_ONKEY
5V_AO_ONKEY
SN 74LVC1G74
DQER-DFN08
SD* VCC
D Q
CP Q*
RD GND
D
G
S
5V_AO_ONKEY
10kΩ,1%
D
G
S
I/O Type
Input (debounced)
Input (debounced)
L62 Input
L60 Input
L52 Input
Input
Output
L54 Output
L61 Output
5V_AO_ONKEY
100kΩ,1%
0.1uF
240Ω,1%
G
D
G 0.47uF
S
0.1uF
D
G
S
5V_AO 5V_AO_ONKEY
Trigger Drive Description
Level Mode
Level OD (HiZ) Power Button
Edge OD (HiZ) Determine when USB power is supplied
Level OD (HiZ) Closed loop on power output
Edge OD (HiZ) Monitor / Power Good mask
Level OD (HiZ) Triggers shutdown sequence
OD (HiZ) Strap pin for board selection
PP Enable power to module
PP Enable input to PMIC
OD Buffered output of power button signal
Optional ACOK circuit Output
D
S
DG-09840-001_v2.5 | 24
Power
See note
MCU Pin
P0.0
P0.6
P0.7
P1.1
P1.0
P1.2
P1.3
P1.5
P1.6