Table 7-4. Pcie Clock And Control Pin Descriptions - Nvidia Jetson AGX Xavier Series Design Manual

Pin # Module Pin Name
C31 NVHS0_SLVS_RX6_P
A31 NVHS0_SLVS_RX7_N
A30 NVHS0_SLVS_RX7_P
H25 NVHS0_TX0_N
H24 NVHS0_TX0_P
K24 NVHS0_TX1_N
K25 NVHS0_TX1_P
G26 NVHS0_TX2_N
G27 NVHS0_TX2_P
J27 NVHS0_TX3_N
J26 NVHS0_TX3_P
H29 NVHS0_TX4_N
H28 NVHS0_TX4_P
K28 NVHS0_TX5_N
K29 NVHS0_TX5_P
G30 NVHS0_TX6_N
G31 NVHS0_TX6_P
J31 NVHS0_TX7_N
J30 NVHS0_TX7_P
Notes:
1. In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals.
Table 7-4. PCIe Clock and Control Pin Descriptions
Pin # Module Pin SoC Signal
Name
E14 PEX_CLK0_N PEX_CLK0N
E15 PEX_CLK0_P PEX_CLK0P
E11 PEX_L0_ PEX_L0_
CLKREQ_N CLKREQ_N
D10 PEX_L0_RST_N PEX_L0_RST_N
F17 PEX_CLK1_N PEX_CLK1N
F16 PEX_CLK1_P PEX_CLK1P
D9 PEX_L1_ PEX_L1_
CLKREQ_N CLKREQ_N
B9 PEX_L1_RST_N PEX_L1_RST_N
F21 PEX_CLK3_N PEX_CLK3N
F20 PEX_CLK3_P PEX_CLK3P
J10 PEX_L3_ PEX_L3_
CLKREQ_N CLKREQ_N
K9 PEX_L3_RST_N PEX_L3_RST_N
E22 PEX_CLK4_N PEX_CLK4N
E23 PEX_CLK4_P PEX_CLK4P
G8 PEX_L4_ PEX_L4_
CLKREQ_N CLKREQ_N
J9 PEX_L4_RST_N PEX_L4_RST_N
F25 PEX_CLK5_N PEX_CLK5N
F24 PEX_CLK5_P PEX_CLK5P
C8 PEX_L5_ PEX_L5_
CLKREQ_N CLKREQ_N
Jetson AGX Xavier Series Product
SoC Signal Usage/Description
NVHS0_RX6_P PCIe/SLVS 0 Receive Lane 6. PCIe x8
controller #5 or SLVS, lane 6.
NVHS0_RX7_N PCIe/SLVS 0 Receive Lane 7. PCIe x8
controller #5 or SLVS, lane 7.
NVHS0_RX7_P
NVHS0_TX0_N PCIe Transmit Lane 0. PCIe x8 controller
#5, lane 0.
NVHS0_TX0_P
NVHS0_TX1_N PCIe Transmit Lane 1. PCIe x8 controller
#5, lane 1.
NVHS0_TX1_P
NVHS0_TX2_N PCIe Transmit Lane 2. PCIe x8 controller
#5, lane 2.
NVHS0_TX2_P
NVHS0_TX3_N PCIe Transmit Lane 3. PCIe x8 controller
#5, lane 3.
NVHS0_TX3_P
NVHS0_TX4_N PCIe Transmit Lane 4. PCIe x8 controller
#5, lane 4.
NVHS0_TX4_P
NVHS0_TX5_N PCIe Transmit Lane 5. PCIe x8 controller
#5, lane 5.
NVHS0_TX5_P
NVHS0_TX6_N PCIe Transmit Lane 6. PCIe x8 controller
#5, lane 6.
NVHS0_TX6_P
NVHS0_TX7_N PCIe Transmit Lane 7. PCIe x8 controller
#5, lane 7.
NVHS0_TX7_P
Usage/Description
PCIe 0 Reference Clock for controller #0.
PCIe 0 Clock Request for controller #0. Pulled
to 3.3V through 47kΩ resistor on-module.
PCIe 0 Reset for controller #0. Pulled to 3.3V
through 4.7kΩ resistor on-module.
PCIe 1 Reference Clock for controller #1.
PCIe 1 Clock Request for controller #1. Pulled
to 3.3V through 47kΩ resistor on-module.
PCIe 1 Reset for controller #1. Pulled to 3.3V
through 4.7kΩ resistor on-module.
PCIe 3 Reference Clock for controller #3.
PCIe 3 Clock Request for controller #3. Pulled
to 3.3V through 47kΩ resistor on-module.
PCIe 3 Reset for controller #3. Pulled to 3.3V
through 4.7kΩ resistor on-module.
PCIe 4 Reference Clock for controller #4,
PCIe 4 Clock Request for controller #4. Pulled
to 3.3V through 47kΩ resistor on-module.
PCIe 4 Reset for controller #4. Pulled to 3.3V
through 4.7kΩ resistor on-module.
PCIe 5 Reference Clock for controller #5 when
Jetson AGX Xavier is Root Port. Unused when
Jetson AGX Xavier used as Endpoint.
PCIe 5 Clock Request for controller #5. Input
when Jetson AGX Xavier is Root Port. Output
USB, PCIe, and UFS
Usage on NVIDIA Direction
Carrier Board
Output
Usage on NVIDIA Direction
Carrier Board
M.2 Key M Connector Output
Input
Output
eSATA Bridge Output
Unused Input
eSATA Bridge Output
M.2 Key E Connector Output
Input
Output
Unused Output
Input
Output
PCIe x16 Connector Output
Input
DG-09840-001_v2.5 | 39
Pin Type
UPHY Diff Pair
Pin Type
PCIe Diff Pair
Open-Drain –
3.3V
PCIe Diff Pair
Open-Drain –
3.3V
Diff pair
Open-Drain –
3.3V
Diff pair
Open-Drain –
3.3V
Diff pair
Open-Drain –
3.3V