Table of Contents
Advertisement
Module Pin
Type
Name (other)
NVDBG_SEL
15.2.2
Debug UART
Jetson AGX Xavier provides UART3_DEBUG for debug purposes. The connections are
described in the following table.
Table 15-3.
Debug UART Connections
Module Pin Name
Type
UART3_TX_DEBUG
O
UART3_RX_DEBU
I
G
15.3
Strapping Pins
Jetson AGX Xavier has one strap (
board. That strap is used to enter Force Recovery mode (held low during power-on). The other
straps mentioned in this section are for use on the module by NVIDIA only. Their state at
power-on must not be affected by any connections on the carrier board. The carrier board
design should guarantee a high-z on the pins during boot. The pins that are associated with
SoC straps (besides
FORCE_RECOVERY_N
Table 15-4.
Strapping Pins
Pin #
Pin Name
L10
FORCE_RECOVERY_N
E10
GPIO12
L11
STANDBY_REQ_N
L4
UART4_RTS
L5
UART4_TX
K53
UART1_TX
K58
UART1_RTS
K58
UART5_RTS
Jetson AGX Xavier Series Product
Termination
100kΩ to GND on module
Termination
If level shifter implemented, 100kΩ to supply
on the non-Jetson AGX Xavier side of the
device.
FORCE_RECOVERY_N
) are as follows:
Description
USB Recovery Strap
Boot Chain Select (JAXi only – See
On-Module use only
"
"
"
"
"
Description
NVIDIA Debug Select: Used as select
Normal operation: Leave series resistor from NVDBG_SEL not
stuffed.
Advanced Debug modes: Connect NVDBG_SEL to VDD_1V8
(install 0Ω resistor as shown).
Description
UART Transmit: Connect to RX pin
of serial device
UART Receive: Connect to TX pin
of serial device
) that is intended to be used on the carrier
Table 15-4
Debug and Strapping
)
DG-09840-001_v2.5 | 119
Advertisement
Table of Contents
