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Figure 10-2.
Camera CSI D-PHY Connections
Jetson AGX Xavier
SoC
CSI
CSI_A_CLK_N
CSI_A_CLK_P
CSI_A_D0_N
CSI_A_D0_P
CSI_A_D1_N
CSI_A_D1_P
CSI_B_CLK_N
CSI_B_CLK_P
CSI_B_D0_N
CSI_B_D0_P
CSI_B_D1_N
CSI_B_D1_P
CSI_C_CLK_N
CSI_C_CLK_P
CSI_C_D0_N
CSI_C_D0_P
CSI_C_D1_N
CSI_C_D1_P
CSI_D_CLK_N
CSI_D_CLK_P
CSI_D_D0_N
CSI_D_D0_P
CSI_D_D1_N
CSI_D_D1_P
CSI_E_CLK_N
CSI_E_CLK_P
CSI_E_D0_N
CSI_E_D0_P
CSI_E_D1_N
CSI_E_D1_P
CSI_F_CLK_N
CSI_F_CLK_P
CSI_F_D0_N
CSI_F_D0_P
CSI_F_D1_N
CSI_F_D1_P
CSI_G_CLK_N
CSI_G_CLK_P
CSI_G_D0_N
CSI_G_D0_P
CSI_G_D1_N
CSI_G_D1_P
CSI_H_CLK_N
CSI_H_CLK_P
CSI_H_D0_N
CSI_H_D0_P
CSI_H_D1_N
CSI_H_D1_P
Note: Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the
timing and Vil/Vih requirements at the receiver and maintain signal quality and meet
requirements for the frequencies supported by the design.
Jetson AGX Xavier Series Product
CSI0_CLK_N
F42
CSI0_CLK_P
F43
CSI0_D0_N
E41
CSI0_D0_P
E42
CSI0_D1_N
E38
CSI0_D1_P
E39
CSI1_CLK_N
H42
CSI1_CLK_P
H43
CSI1_D0_N
G42
CSI1_D0_P
G41
CSI1_D1_N
J42
CSI1_D1_P
J41
CSI2_CLK_N
B4 2
CSI2_CLK_P
B4 3
CSI2_D0_N
A42
CSI2_D0_P
A41
CSI2_D1_N
C41
CSI2_D1_P
C42
CSI3_CLK_N
F45
CSI3_CLK_P
F46
CSI3_D0_N
E44
CSI3_D0_P
EMI
E45
CSI3_D1_N
G45
&
CSI3_D1_P
G44
ESD
CSI4_CLK_N
F49
CSI4_CLK_P
F48
CSI4_D0_N
G47
CSI4_D0_P
G48
CSI4_D1_N
E48
CSI4_D1_P
E47
CSI5_CLK_N
C45
CSI5_CLK_P
C44
CSI5_D0_N
D43
CSI5_D0_P
D42
CSI5_D1_N
D45
CSI5_D1_P
D46
CSI6_CLK_N
J45
CSI6_CLK_P
J44
CSI6_D0_N
K43
CSI6_D0_P
K44
CSI6_D1_N
H45
CSI6_D1_P
H46
CSI7_CLK_N
B4 6
CSI7_CLK_P
B4 5
CSI7_D0_N
A45
CSI7_D0_P
A44
CSI7_D1_N
C48
CSI7_D1_P
C47
2-Lane
4-Lane (1_CLK
not used)
2-Lane
2-Lane
4-Lane (3_CLK
not used)
2-Lane
2-Lane
4-Lane (5_CLK
not used)
2-Lane
4-Lane (7_CLK
not used)
DG-09840-001_v2.5 | 85
Video Input
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