Mpmc Periphid3 Register, Offset Fech; Mpmc Primecellid Register, Offset 00H; Mpmc Pcellid0 Register, Offset Ff0H - ADMtek ADM5120 Datasheet

ADM5120

4.7.35 MPMC PeriphID3 register, offset FECh

Bit # Type Name
2:0 R Configuration
5:3 R Configuration
6 R Configuration
7 R Configuration
31:8 Reserved
Note:
The MPMCPeriphID2 register is hard-coded and the fields within the register determine the reset value.

4.7.36 MPMC PrimeCellID register, offset 00h

Bit # Type Name
7:0 R
15:8 R
23:16 R
31:24 R

4.7.37 MPMC PCellID0 register, offset FF0h

Bit # Type Name
7:0 R
31:8 Reserved
ADMtek Inc.
Descriptions
Indicates the number of AHB slave ports:
000=1 AHB slave port
001=2 AHB slave port
010=4 AHB slave port
011=6 AHB slave port
100=8 AHB slave port
101-111=reserved
For PL172 this field is set to 010.
Indicates the AHB master bus width:
000=32-bit wide
001=64-bit wide
010=128-bit wide
011=256-bit wide
100=512-bit wide
101=1024-bit wide
110-111=reserved
For PL172 this field is set to 000.
Data buffers:
0=no
1=yes
For PL172 this field is set to 1.
TIC interface:
0=no
1=yes
For PL172 this field is set to 1.
Read undefined, must be written as zeros.
Descriptions
The reset value = 0x0D (held by MPMCPCellID0).
The reset value = 0xF0 (held by MPMCPCellID1).
The reset value = 0x05 (held by MPMCPCellID2).
The reset value = 0xB1 (held by MPMCPCellID3).
Descriptions
These bits read back as 0x0D.
Read undefined, must be written as zeros.
Register Description
Initial Value
010
0
1
1
Initial Value
0D
F0
05
B1
Initial Value
0D
4-51