ADM5120
DWORD 1 – Data Buffer Pointer
Bit
31-0
DWORD 2 – CONTROL/BUF Length
Bit
31-17
16
15-0
DWORD 3 – Next Transfer Descriptor Pointer
Bit
31-4
3-0
3.5.3 DMA operation
To provide a high-performance and effective way for software packet scheduling, the
DMA is able to handle both transmit and receive packets in a single descriptor chain. In
the endpoint and transfer descriptors, the software can specify the descriptor format
(Isochronous or none-Isochronous), direction, speed, and data toggle bit.
If there is any isochronous or periodic data that needs to be transmitted/received, this
descriptor needs to link at the beginning of the link list to guarantee the bus bandwidth.
After these descriptors, the control or bulk descriptor is linked.
DMA starts to access the first descriptor in the link list and transmit/receive the data
through the USB bus. Since there might be several USB packets segmented in one
descriptor. After one USB packet is transmitted, DMA will update the transmit status,
data length, start address of the data buffer, and length of data buffer for further
access, and advance to the next descriptor.
When the DMA finishes it's transmit/receive of a descriptor, it depends on the setting of
the interrupt enable to generate HC_INT to indicate this descriptor is ready for the
software driver process.
If all the descriptors have been accessed once, and the frame is not yet over, then the
DMA will try to access the general descriptor again in order to get a high performance.
ADMtek Inc.
Description
Starting address of the data buffer
This field indicates the starting address of the data buffer. Data buffer may be aligned on
any byte. When an OUT or SETUP packet has been transmitted, this field will be
updated as the next start address of the data buffer.
Description
Reserved
Interrupt enable
This field indicates that whether the interrupt will be asserted when this descriptor is
completed.
Length of data buffer
This field indicates the length of the current data buffer.
Description
Starting address of the next descriptor in host memory space
Reserved
Function Description
3-14
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