ADMtek ADM5120 Datasheet page 7

ADMtek Inc.
4.4.46
4.4.47
4.4.48
4.4.49
4.4.50
4.4.51
4.4.52
4.4.53
4.4.54
4.4.55
4.4.56
4.4.57
4.4.58
4.4.59
4.4.60
4.4.61
4.4.62
4.4.63
4.4.64
4.4.65
4.4.66
4.4.67
4.4.68
4.4.69
4.5 USB C
4.6 USB C
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.6.10
4.6.11
4.6.12
4.6.13
4.7 MPMC R
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
ADM5120
Int_mask, offset 0xB4 ............................................................................. 4-21
GPIO_conf0, offset 0xB8 ....................................................................... 4-22
GPIO_conf2, offset 0xBc ....................................................................... 4-22
Watchdog0, offset 0xC0 ......................................................................... 4-22
Watchdog1, offset 0xC4 ......................................................................... 4-22
Swap_in, offset 0xC8.............................................................................. 4-23
Swap_out, offset 0xCc............................................................................ 4-23
send_Hbaddr, offset 0xD0 ..................................................................... 4-23
send_Lbaddr, offset 0xD4 ...................................................................... 4-23
receive_Hbaddr, offset 0xD8 ................................................................. 4-23
receive_Lbaddr, offset 0xDc .................................................................. 4-24
send_Hwaddr, offset 0xE0 ..................................................................... 4-24
send_Lwaddr, offset 0xE4...................................................................... 4-24
receive_Hwaddr, offset 0xE8 ................................................................. 4-24
receive_Lwaddr, offset 0xEc.................................................................. 4-24
Timer_int, offset 0xF0............................................................................ 4-24
Timer, offset 0xF4 .................................................................................. 4-25
Reserved, offset 0xF8 ............................................................................. 4-25
Reserved, offset 0xFc ............................................................................. 4-25
port0_LED, offset 0x100........................................................................ 4-25
port1_LED, offset 0x104........................................................................ 4-25
port2_LED, offset 0x108........................................................................ 4-25
port3_LED, offset 0x10c ........................................................................ 4-26
port4_LED, offset 0x110........................................................................ 4-26
S R
ONTROL TATUS EGISTER
S R
ONTROL TATUS EGISTERS
General Control , offset 0x00................................................................. 4-27
Interrupt Status, offset 0x04................................................................... 4-27
Interrupt Enable, offset 0x08 ................................................................. 4-28
Reserved, offset 0x0C............................................................................. 4-28
Host General Control, offset 0x10 ......................................................... 4-29
Reserved, offset 0x14 ............................................................................. 4-29
SOF Frame interval, offset 0x18............................................................ 4-29
SOF Frame number, offset 0x1C ........................................................... 4-30
Reserved, offset 0x20 - 0x6C ................................................................. 4-30
Low speed threshold, offset 0x70 ........................................................... 4-30
RH descriptor, offset 0x74 ..................................................................... 4-31
Port x status, offset 0x78........................................................................ 4-33
Host Descriptor Head Starting Address, offset 0x80............................. 4-36
............................................................................................. 4-36
EGISTERS
MPMC Registers Summary.................................................................... 4-36
MPMC Control register, offset 000h ..................................................... 4-38
MPMC Status register, offset 004h........................................................ 4-38
MPMC Config register, offset 008h....................................................... 4-39
MPMC Dynamic Control register, offset 020h...................................... 4-39
MPMC Dynamic Refresh register, offset 024h ...................................... 4-40
M ............................................................. 4-26
AP
D .............................................. 4-27
ESCRIPTION
V1.13
iv