Memory Bus Write Timing - ADMtek ADM5120 Datasheet

ADM5120

5.3.3 Memory Bus Write Timing

ROM/FLASH/External Memory: Zero Wait state Timing
CLK_OUT
ADDR[19:0]
DATA[31:0]
F_CSX_N
WE_N
ROM/FLASH/External Memory: Two Wait state WriteTiming
CLK_OUT
ADDR[19:0]
DATA[31:0]
F_CSX_N
WE_N
ROM/FLASH/External Memory: Two Write enable delay state WriteTiming
CLK_OUT
ADDR[19:0]
DATA[31:0]
F_CSX_N
WE_N
Notes: T is the period of CLK_OUT (11.5ns/87.5Mhz)
Item
tASU
tWDSU
tWDH
tWEP
ADMtek Inc.
Address
Data
1T
1T
Address
Data
Address
Data
2T
3T
Description
Adress/CS to WE_N falling setup time
Data to WE_N rising setup time
Data to WE_N rising hold time
WE_N pulse width
1T
3T
Min
--
--
--
--
Electrical Specification
Typ Max
(n+1)T --
(n+1)T --
1T --
(n+1)T --
5-6