Usb 1.1 Host Controller; Block Diagram; System Bus Interface; Operational Register - ADMtek ADM5120 Datasheet

ADM5120
3.4

USB 1.1 Host Controller

3.4.1 Block Diagram

The following block diagram describes the functional blocks of the ADMtek USB 1.1
Host controller.

3.4.2 System bus interface

This block provides the USB Host controller with the connection to the AHB bus
interface. The AHB bus is a 32-bit wide data bus, high-performance pipeline architecture.
This block contains the AHB master interface and slave interface. Host can program the
USB Host controller operational register via the AHB slave interface. The DMA units
within the USB Host controller will act as bus masters and access the system memory
through the AHB master interface.

3.4.3 Operational Register

This block is the CSR (configure and status register) of USB 1.1 Host controller. The
local host configures USB 1.1 Host controller via these registers. It includes DMA,
endpoint, enable/disable, and interrupt control. The local host gets the status of the USB
1.1 Host controller by reading the registers. It includes the DMA, interrupt and USB bus
ADMtek Inc.

Figure 3-1 Block Diagram of ADMtek USB 1.1 Host controller

Function Description
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