ADM5120
4.8.3 UART receive status register/error clear register, offset 04h
Bit #
Type
Name
0
R
FE
1
R
PE
2
R
BE
3
R
OE
6:4
Reserved
7
W
RSR
4.8.4 UART line control register, high byte, offset 08h
Bit # Type Name
0
R/W
BRK
1
R/W
PEN
2
R/W
EPS
ADMtek Inc.
Descriptions
Framing Error (FE):
When this bit is set to 1, it indicates that the received
character did not have a valid stop bit.
Parity Error (PE):
When this bit is set to 1, it indicates that the parity of
received data character does pot match the parity
selected in UARTLCR_H (bit 2)
Break Error (BE):
This bit is set to 1 if a break condition was detected,
indicating that the received data input was held LOW
for longer than a full-word transmission time.
Overrun Error (OE):
This bit is set to 1 if data is received and the FIFO is
already full.
Not Applicable
A write to this register clears the framing, parity, break
and overrun errors. The data value is not important.
Descriptions
Send Break:
If this bit is set to 1, a low level is continually output
on the UARTTXD output, after completing
transmission of the current character. This bit must be
asserted for at least one complete frame transmission
time in order to generate a break condition. The
transmit FIFO contents remain unaffected during a
break condition.
For normal use, this bit must be cleared to 0.
Parity enable:
If this bit is set to 1, parity checking and generation is
enabled, else parity is disabled and no parity bit assed
to the data frame.
Even Parity Select:
If this bit is set to 1, even parity generation and
checking is performed during transmission and
reception, which checks for an even number of 1s in
data and parity bits. When cleared to 0 then odd parity
is performed which checks for an odd number of
1s.this bit has no effect when parity is disabled by
parity enable being cleared to 0.
Register Description
Initial Value
0
0
0
0
0
Initial Value
0
0
0
4-53
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