ADM5120
14
RW
RD_cmd
15
Reserved
31:16 RW
WT_data
4.4.28 PHY_cntl1, offset 0x6c
Bits
Type
Name
0
RO
WT_done
1
RO
RD_rdy
15:2
Reserved
31:16 RO
RD_data
4.4.29 FC_th, offset 0x70
Bits
Type
Name
7:0
RW
Drop2_set
15:8
RW
Drop2_rls
24:16 RW
FC_set
31:25
Reserved
Note: The working global thresholds = (register value) * 2, The Drop1_set[7:0] threshold default value =
137 blocks, The default working Drop1_set threshold = 137 x 2 =274.
4.4.30 adj_port_th, offset 0x74
Bits
Type
Name
3:0
RW
adj_port_th_H
7:4
RW
adj_port_th_L
15:8
Reserved
24:16 RW
FC_rls
31:25
Reserved
4.4.31 Port_th, offset 0x78
Bits
Type
Name
7:0
RW
per_port_th
15:8
RW
CPU_th
23:16 RW
CPU_hold_th
31:24 RW
CPU_rls_th
Note: Suggestion value is 0xE8DC1818h.
4.4.32 PHY_cntl2, offset 0x7c
Bits
Type
Name
4:0
RW
Auto-negotiation Auto-negotiation enable. 1: Enable
9:5
RW
Speed
14:10 RW
Duplex
ADMtek Inc.
Read command, self_clear
Not Applicable
The data be written into the PHY
Description
Write operation is done, read_clear
Read operation is complete and data is ready, read_clear
Not Applicable
The read data
Description
Switch drop2 set threshold
Switch drop2 release threshold
Switch flow control set threshold
Not Applicable
Description
per_port guaranteed normal priority pkt
per_port guaranteed high priority pkt
Not Applicable
Switch flow control release threshold
Not Applicable
Description
per port buffer threshold
CPU port buffer threshold
the CPU hold threshold for all ports
block
the CPU hold release threshold
Description
Speed control. 1: 100M 0: 10M
Duplex control. 1: Full 0: Half
106 free blocks
→
134 free blocks
→
220 free blocks
→
3 blocks
→
3 blocks
→
268 free blocks
→
13 occupied blocks
→
48 occupied blocks
→
default 120 free
→
default 132 free block
→
Register Description
Initial value
Initial value
Initial value
Initial value
Initial value
4-16
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