Memory Bus Read Timing - ADMtek ADM5120 Datasheet

ADM5120

5.3.2 Memory Bus Read Timing

ROM/FLASH/External Memory: Two wait state Read Timing
CLK_OUT
ADDR[19:0]
DATA[31:0]
F_CSX_N
F_OE_N
ROM/FLASH/External Memory: Two Output enable delay state Read Timing
CLK_OUT
ADDR[19:0]
DATA[31:0]
F_CSX_N
F_OE_N
Notes: T is the period of CLK_OUT (11.5ns/87.5Mhz)
Item
tRDSU
tRDH
tAC
tAOE
ADMtek Inc.
Address
3T
Address
2T
Description
Data to CLK_OUT rising setup time
Data to CLK_OUT rising hold time
Address/F_CSX_N pulse width
Address/F_CSX_N to F_OE_N setup
Data
tDSU
Data
1T
Min
TBD
TBD
--
--
Electrical Specification
Typ Max
-- --
-- --
(n+1)T --
nT --
5-5