Irq_Raw_Status, Offset: 0X40; Irq_Enable, Offset: 0X80; Irq_Enable_Clear, Offset: 0Xc0; Reserved, Offset: 0X10 - ADMtek ADM5120 Datasheet

ADM5120

4.2.4 IRQ_raw_status, offset: 0x40

Bits Type Name
9:0 RO IRQ_raw_status[7
:0]
31:10 RO Reserved

4.2.5 IRQ_enable, offset: 0x80

Bits Type Name
9:0 RW IRQ_enable[7:0]
31:10 RO Reserved

4.2.6 IRQ_enable_clear, offset: 0xc0

Bits Type Name
9:0 RW IRQ_enable_clear
[7:0]
31:10 Reserved

4.2.7 Reserved, offset: 0x10

Bits Type Name
31:0 Reserved

4.2.8 INT_Mode, offset: 0x14

Bits Type Name
9:0 RW INT_mode[9:0]
31:10 Reserved
ADMtek Inc.
Description
The status of the interrupt sources before
masking.
1: the corresponding IRQ is active
Not Applicable
Description
The enable register is used to mask the
interrupt source.
1: enable the interrupt and allow the
interrupt request to MIPS.
Writing "0" has no effect.
Not Applicable
Description
The clear bits of the IRQ_enable.
Writing "1" clear the corresponding bit of
IRQ_enable.
Writing "0" has no effect.
Not Applicable
Description
Not Applicable
The interrupt type of the interrupt sources
.
1: the corresponding Interrupt port
generate the FIQ to MIPS
0: the corresponding Interrupt port
generate the IRQ to MIPS
Not Applicable
Register Description
Initial value
0
0
Initial value
0
0
Initial value
0
Initial value
Initial value
0
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