ADM5120
Bit # Type Name
4
R/W
RIE
5
R/W
TIE
6
R/W
RTIE
7
Reserved
4.8.8 UART flag register (UARTFR), offset 18h
Bit #
Type
Name
0
RO
CTS
1
RO
DSR
ADMtek Inc.
Descriptions
Modem status change when one of the following
events occurs:
(1) 0 → 1
(2) 1 → 0
Receive interrupt enable:
If this bit is set to 1, the receive interrupt is enabled.
Thereceive interrupt changes state when one of the
following events occurs:
1.if the FIFOs are enabled and the receive FIFO is half
or more full, then the receive interrupt is asserted
HIGH. It is cleared by reading data from the receive
FIFO until it becomes less than half full.
2.if the FIFOs are disabled and data is received thereby
filling the location, the receive interrupt is asserted
HIGH. The receive interrupt is cleared by performing a
single read to the receive FIFO.
Transmit interrupt enable:
If this bit is set to 1, the transmit interrupt is enabled.
The transmit interrupt changes state when one of the
following events occurs:
1.if the FIFOs are enabled and the transmit FIFO is at
least half empty, then the transmit interrupt is asserted
HIGH. It is cleared by filling the transmit FIFO to
more than half full.
2.if the FIFOs are disabled and there is no data preset
in the transmitters single location, the transmit FIFO is
asserted HIGH. It is cleared by performing a single
write to the transmitter FIFO.
Receive timeout interrupt enable:
If this bit is set to 1, the receive timeout interrupt is
enabled.
The receive timeout interrupt is asserted when the
receive FIFO is not empty and no further data is
received over a 32-bit period. The receive timeout
interrupt is cleared when the FIFO becomes empty
through reading al the data.
Not Applicable
Descriptions
This bit is the complement of the UART clear to send
(nUARTCTS) modem status input. That is , the bit is 1
when the modem status input is 0.
This bit is the complement of the UART data set ready
Register Description
Initial Value
0
0
0
Initial Value
0
0
4-55
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