ADMtek ADM5120 Datasheet page 5

ADMtek Inc.
3.2.6
3.2.7
3.3 S
WITCH
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.10
3.3.11
3.3.12
3.3.13
3.3.14
3.3.15
3.4 USB 1.1 H
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.5 DMA O
3.5.1
3.5.2
3.5.3
CHAPTER 4 REGISTER DESCRIPTION ................................................................ 4-1
4.1 S
YSTEM
4.2 S
YSTEM AND
4.2.1
4.2.2.
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.3 S
WITCH
4.4 S
WITCH
ADM5120
Stream Cipher Scrambler/ De-scrambler ................................................ 3-3
Encoder/Decoder ..................................................................................... 3-3
E .................................................................................................... 3-4
NGINE
Hashing Function..................................................................................... 3-4
Learning Process ..................................................................................... 3-4
Routing..................................................................................................... 3-4
Forwarding .............................................................................................. 3-4
Buffer Management.................................................................................. 3-5
Flow Control (Patent Pending) ............................................................... 3-5
Full Duplex .............................................................................................. 3-5
Half Duplex.............................................................................................. 3-5
Packet priority and Class of Service (CoS) ............................................. 3-5
VLAN........................................................................................................ 3-6
Address table access ................................................................................ 3-6
Address security ....................................................................................... 3-6
Bandwidth control function...................................................................... 3-7
Send descriptors content .......................................................................... 3-7
Receive descriptors content ..................................................................... 3-8
C .............................................................................. 3-10
OST ONTROLLER
Block Diagram ....................................................................................... 3-10
System bus interface............................................................................... 3-10
Operational Register.............................................................................. 3-10
SIE.......................................................................................................... 3-11
DPLL...................................................................................................... 3-11
Memory BIST ......................................................................................... 3-11
............................................................................................... 3-11
PERATION
Endpoint Descriptor Format.................................................................. 3-11
Transfer Descriptor Format .................................................................. 3-12
DMA operation ...................................................................................... 3-14
M M ........................................................................................ 4-1
EMORY AP
I R
NTERRUPT EGISTERS
Interrupt Control Register Map ............................................................... 4-1
Interrupt Request Source Description ..................................................... 4-1
IRQ_status, offset: 0x00........................................................................... 4-1
IRQ_raw_status, offset: 0x40................................................................... 4-2
IRQ_enable, offset: 0x80 ......................................................................... 4-2
IRQ_enable_clear, offset: 0xc0 ............................................................... 4-2
Reserved, offset: 0x10 .............................................................................. 4-2
INT_Mode, offset: 0x14 ........................................................................... 4-2
FIQ_status, offset: 0x18........................................................................... 4-3
IRQ_test_source, offset: 0x1c .................................................................. 4-3
IRQ_source_sel, offset: 0x20 ................................................................... 4-3
INT_level, offset: 0x24 ............................................................................. 4-3
C R M
ONTROL EGISTER
C R D
ONTROL EGISTER
.................................................................... 4-1
........................................................................ 4-4
AP
.......................................................... 4-5
ESCRIPTION
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