Interrupt Enable, Offset 0X08; Reserved, Offset 0X0C - ADMtek ADM5120 Datasheet

ADM5120
Bits Type Name
C
10 R/W1 SO
C
11 R/W1 FNO
C
19:12 R/W1 Reserved
C
20 R/W1 TD_Complete
C
25:21 R/W1 Reserved
C
28:26 RO Reserved
29 R/W1 SW_INT
C
30 R/W1 FATAL_INT
C
31 RO INT_ACT

4.6.3 Interrupt Enable, offset 0x08

Bits Type Name
30:0 R/W INT_MASK
31 R/W INT_EN

4.6.4 Reserved, offset 0x0C

Bits Type Name
ADMtek Inc.
Description
1: Detected device insertion or remove. This bit will
only be set for the device or hub, which is attached to
host directly.
Scheduling overrun
This bit is set when USB schedules for current frame
overruns.
Frame number overflow
This bit is set when the MSB of the frame number
changes.
Not Applicable
A TD is completed.
Not Applicable
Not Applicable
Software interrupt, Both modes:
1: Software Interrupt. This bit is set when software set
one to SW_INT_REQ 0x00, and is cleared after
software writes one to this bit.
Fatal interrupt, Device mode:
Reserved.
Host mode:
1:Fatal system bus error occurs.
Interrupt active
When this bit is set, it indicates that at least one
unmasked interrupt status is set.
Description
Interrupt mask
Bits are set to allow the corresponding interrupts (bit
21:0 in Interrupt Status register) to generate an interrupt
request. And cleared to prevent the interrupt from
happening.
Interrupt enable
1: Enable the controller to assert interrupt,
0: Disable the controller to assert interrupt.
Description
Register Description
Initial value
0
0
0
0
0
0
0
0
0
Initial value
0
0
Initial value
4-28