Mpmc Static Wait Rd [0,1,2,3] Register; Mpmc Static Wait Page [0,1,2,3] Register; Mpmc Static Wait Wr [0,1,2,3] Register - ADMtek ADM5120 Datasheet

ADM5120
Note:
The delay is WAITOEN x tHCLK.

4.7.24 MPMC Static Wait Rd [0,1,2,3] register

Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2
respectively
Bit # Type Name
4:0 R/W WAITRD
31:5 Reserved
Note:
For non-sequential reads, the wait state time is (WAITRD+1) x tHCLK.

4.7.25 MPMC Static Wait Page [0,1,2,3] register

Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2
respectively
Bit # Type Name
4:0 R/W WAITPAGE
31:5 Reserved
Note:
For asynchronous page mode read for sequential reade,the wait state time for page mode
accesses after the first read is (WAITPAGE+1) x tHCLK.

4.7.26 MPMC Static Wait Wr [0,1,2,3] register

Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2
respectively
Bit # Type Name
4:0 R/W WAITWR
ADMtek Inc.
Descriptions
Nonpage mode read wait states or asynchronous page
mode read first access wait state.
Nonpage mode:
00000 to 11110 = (n+1) HCLK cycles for read
accesses
11111 = 32 HCLK cycles for read accesses(reset value
on nPOR).
Asynchronous page mode read, first read only:
00000 to 11110 = (n+1) HCLK cycles for burst read
accesses
11111 = 32 HCLK cycles for page read accesses (reset
value on nPOR)
Read undefined, must be written as zeros.
Descriptions
Asynchronous page mode read after the first access
wait states: number of wait states for asynchronous
page mode read accesses after the first read.
00000 to 11110 = (n+1) HCLK cycle read access time
11111 = 32 HCLK cycle read access time (reset value
on nPOR).
Read undefined, must be written as zeros.
Descriptions
Write wait states: SRAM wait state time for write
accesses after the first read.
Register Description
Initial Value
11111
Initial Value
11111
Initial Value
11111
4-48