Mpmc Control Register, Offset 000H; Mpmc Status Register, Offset 004H - ADMtek ADM5120 Datasheet

ADM5120

4.7.2 MPMC Control register, offset 000h

Bit # Type Name
0 R/W E
1 R/W M
2 R/W L
3 R/W D
31:4 Reserved

4.7.3 MPMC Status register, offset 004h

Bit # Type Name
0 R B
ADMtek Inc.
Offset Register
FF0 MPMCPCellID0
FF4h MPMCPCellID1
FF8h MPMCPCellID2
FFCh MPMCPCellID3
Descriptions
MPMC Enable: indicates if the PrimeCell MPMC is
enabled or disabled.
0 = disabled
1 = enabled (reset value on nPOR, and HRESETn).
Disabling the PrimeCell MPMC reduces power
consumption. When the memory controller is disabled
the memory is not refreshed. The memory controller is
enabled by setting the enable bit, or by system, or power-
on reset.
Address mirror: indicates normal or reset memory map.
0 = normal memory map
1 = reset meory map. Static memory chip select 1 is
mirrorred onto chip select 0 and chip select 4 (reset value
on nPOR).
On power-on reset, chip select 1 is mirrorred to both chip
select 0 and chip select 1 and chip 4 memory areas.
Clearing the M bit enables chip select 0 and chip select 4
memory to be accessed.
Low-power mode: indicate normal, or low-power mode.
0 = normal mode (reset value on nPOR, and HRESETn)
1 = low-power mode.
Entering low-power mode reduces memory controller
power consumption. Dynamic memory is refreshed as
necessary. The memory controller returns to normal
function mode by clearing the low-power mode bit (L),
or by system, or power-on reset.
Drain write buffers:
0 = buffers operate normally (reset value on nPOR, and
HRESETn)
1 = drain write buffers.
Not Applicable
Descriptions
Busy: this read-only bit is used to ensure that the
Register Description
Initial Value
1
1
0
0
Initial Value
0
4-38