ADMtek ADM5120 Datasheet page 8

ADMtek Inc.
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4.8 UART R
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CHAPTER 5 ELECTRICAL SPECIFICATION....................................................... 5-1
5.1 A
BSOLUTE
ADM5120
MPMC Dynamic RP register, offset 030h ............................................. 4-40
MPMC Dynamic RAS register, offset 034h ........................................... 4-41
MPMC Dynamic SREX register, offset 038h......................................... 4-41
MPMC Dynamic APR register, offset 03Ch .......................................... 4-41
MPMC Dynamic DAL register, offset 040h........................................... 4-41
MPMC Dynamic WR register, offset 044h ............................................ 4-41
MPMC Dynamic RC register, offset 048h ............................................. 4-42
MPMC Dynamic RFC register, offset 04Ch .......................................... 4-42
MPMC Dynamic XSR register, offset 050h ........................................... 4-42
MPMC Dynamic RRD register, offset 054h .......................................... 4-42
MPMC Dynamic MRD register, offset 058h.......................................... 4-42
MPMC Static Extended Wait register, offset 080h ................................ 4-43
MPMC Dynamic Config [0,1,2,3] register............................................ 4-43
MPMC Dynamic Ras Cas[0,1,2,3] register........................................... 4-46
MPMC Static Config[0,1,2,3] register .................................................. 4-46
MPMC Static Wait Wen [0,1,2,3] register ............................................ 4-47
MPMC Static Wait Oen[0,1,2,3] register.............................................. 4-47
MPMC Static Wait Rd [0,1,2,3] register ............................................... 4-48
MPMC Static Wait Page [0,1,2,3] register ........................................... 4-48
MPMC Static Wait Wr [0,1,2,3] register............................................... 4-48
MPMC Static Wait Turn [0,1,2,3] register............................................ 4-49
Conceptual MPMC Additional Peripheral ID register ......................... 4-49
MPMC PeriphID4 register, offset FD0h ............................................... 4-49
MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh.................... 4-50
Conceptual MPMC Peripheral ID register ........................................... 4-50
MPMC PeriphID0 register, offset FE0h................................................ 4-50
MPMCPeriphID1 register, offset FE4h................................................. 4-50
MPMC PeriphID2 register, offset FE8h................................................ 4-50
MPMC PeriphID3 register, offset FECh ............................................... 4-51
MPMC PrimeCellID register, offset 00h ............................................... 4-51
MPMC PCellID0 register, offset FF0h ................................................. 4-51
MPMC PCellID1 register, offset FF4h ................................................. 4-52
MPMCPCellID2 register, offset FF8h .................................................. 4-52
MPMCPCellID3 register, offset FFCh.................................................. 4-52
.............................................................................................. 4-52
EGISTERS
Remap and Pause Controller Registers................................................. 4-52
UART data register, offset 00h .............................................................. 4-52
UART receive status register/error clear register, offset 04h ............... 4-53
UART line control register, high byte, offset 08h .................................. 4-53
UART line control register, middle byte, offset 0ch............................... 4-54
UART line control register, low byte, offset 10h ................................... 4-54
UART control register (UARTCR), offset 14h ....................................... 4-54
UART flag register (UARTFR), offset 18h............................................. 4-55
UARTIIR/UARTICR, offset 1ch ............................................................. 4-57
M R
AXIMUM ATINGS
........................................................................... 5-1
V1.13
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